Logic Circuit Interface Arrangements TRIZ Cases
- GPIO Multiplexing and Level Shifting for Multi-Voltage I/O Buffers
Shared multiplexing and level shifting let GPIO functional blocks work across voltage domains while reducing I/O buffer area.
- Wide-Range IC I/O Circuit with Mode-Selected Voltage Domains
Mode-selected high- and low-voltage I/O paths let one IC interface span 1.08V to 5.5V while preserving timing and reliability.
- Current-Steering Level Shifter for Low-Leakage Multi-Voltage SoCs
A seven-transistor single-N-well level shifter cuts area and Vss leakage in SoCs with small voltage differences between rails.
- Current-Steering Level Shifter for Limited Voltage Differentials
A seven-transistor current-steering topology reduces area and Vss leakage while converting signals across closely spaced voltage domains.
- Cascode Buffer Circuit for Stable Current Across Wide Supply Voltages
A composite high-voltage and low-voltage PMOS buffer stabilizes output current over wide supply swings while limiting NPN over-drive and delay.
- Universal Input Buffer for Single-Ended and Differential Signals
A two-pin buffer uses multiplexing and shared single-ended and differential paths to support LVCMOS, LVDS, LVPECL, and CML while cutting pin count.
- Input Circuit Switching to Prevent Power-Line Current Backflow
A control circuit coordinates pull-up and bulk switches to block pad-to-power-line backflow during power-off and enable correct reset on restart.
- High-Voltage IO Driver Using BJT Buffer in 3V BiCMOS
A boosted voltage rail and BJT buffer enable 5V-capable IO signaling in 3V BiCMOS while preventing transistor overstress at up to 100 MHz.
- Level Shifter Bypass Circuit for Low-Voltage Leakage Control
A bypass path across the load helps level shifters handle near-threshold voltages faster while cutting standby leakage for dynamic voltage scaling.