High-Voltage IO Driver Using BJT Buffer in 3V BiCMOS
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Solution Overview
Problem
The 3V BiCMOS process lacks high voltage devices, making standard CMOS available IO topologies unsuited for 5V supply voltage and 3.3 voltage signaling levels, leading to issues with over-voltage reliability and inability to support fast switching applications like 100 MHz frequency operations.
Innovation Solution
A high voltage IO circuit is implemented using a voltage rail generator circuit and BJT buffer circuit with pull-up and pull-down circuits, coupled with a pad, which generates a voltage rail supply and manages current injection in PNP and NPN transistors to handle input signal transitions, ensuring the pad is charged or discharged appropriately, and using a blocking diode to prevent overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard CMOS IO topologies are used in 3V BiCMOS process, then manufacturing simplicity is maintained, but high voltage signaling capability and over-voltage reliability are lost
Solution Approach 1:
The patent changes the voltage parameters by generating a boosted voltage rail (Vrail) from the available 3V supply using a charge pump circuit. This allows the IO driver to operate at higher voltages (up to 5V) without requiring high voltage transistors, thus maintaining manufacturing simplicity while achieving over-voltage reliability through dynamic voltage adjustment.
Solution Approach 2:
The patent introduces an intermediate voltage rail generator (charge pump circuit) between the 3V supply and the IO driver. This intermediary circuit boosts the voltage dynamically, allowing standard low-voltage transistors to handle high voltage signaling through the generated Vrail, thereby maintaining both ease of manufacture and over-voltage reliability.
2Device complexity
If standard CMOS IO topologies are used in 3V BiCMOS process, then device complexity is reduced, but fast switching capability for 100 MHz operations is lost
Solution Approach 1:
The patent changes the voltage parameter by dynamically boosting the supply voltage to Vrail during switching operations. This higher voltage enables faster charging and discharging of the pad capacitance, achieving 100 MHz switching speeds without increasing device complexity, as the same standard transistors are used with enhanced voltage drive.
3Adaptability or versatility
If high voltage MOS transistors are added to support 5V signaling, then signaling capability is improved, but manufacturing complexity increases due to extra mask-set requirements
Solution Approach 1:
The patent changes the voltage parameter dynamically using a charge pump circuit that generates a boosted voltage rail from the existing 3V supply. This allows standard low-voltage MOS transistors to operate at high voltages temporarily during IO signaling, achieving 5V signaling capability without requiring high voltage MOS transistors or additional mask-sets, thus maintaining ease of manufacture.
Solution Approach 2:
The patent introduces an intermediary charge pump circuit that acts as a voltage translator between the 3V core supply and the high voltage IO interface. This mediator enables standard transistors to handle high voltage signals without requiring specialized high voltage device fabrication, preserving manufacturing simplicity while enhancing signaling capability.
Data Source
AI summary
An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.