Cascode CMOS RF Power Amplifier With Mixed-Oxide Transistors
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Solution Overview
Problem
Designing sub-micron CMOS high-power cascode RF power amplifiers faces challenges such as oxide breakdown, voltage swing limitations, and increased gate resistance with wider unit gate fingers, which affect power gain and linearity.
Innovation Solution
The implementation of a cascode configuration using transistors with different gate oxide thicknesses and lengths, where the second transistor has a thicker gate oxide and longer gate length than the first, combined with bias circuits and amplifier circuits to overcome voltage swing limitations and increase unit gate width without increasing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the unit gate width is increased to achieve high output power, then the drive current increases, but the gate resistance increases excessively which reduces power gain
Solution Approach 1:
The transistor gate is divided into multiple fingers (e.g., 16 fingers) arranged in parallel. Each finger has a smaller individual gate width, but collectively they provide the total required gate width for high drive current. This segmentation reduces the gate resistance of each individual finger while maintaining the total drive current capability, thereby resolving the contradiction between high output power and low gate resistance.
2Power
If the gate length is shortened to benefit from sub-micron CMOS technology, then the power gain increases, but the voltage swing is limited due to oxide breakdown
Solution Approach 1:
The cascode configuration employs two different transistor types with distinct local characteristics: the bottom transistor (M1) has a short gate length (e.g., 40nm) optimized for high gain and frequency performance, while the top transistor (M2) has a long gate length (e.g., 112nm) and thicker oxide designed specifically for high voltage swing capability and oxide breakdown resistance. This local differentiation allows each transistor to optimize its function without compromising the other.
3Power
If the number of gate fingers is increased to achieve high output power, then the drive current increases, but the phase difference between gates increases which reduces power gain
Solution Approach 1:
The gate fingers are arranged in a multi-dimensional layout pattern (e.g., 4 rows of 4 fingers) rather than a simple linear arrangement. This spatial distribution in multiple dimensions reduces the phase difference between adjacent gates by increasing the physical separation and optimizing the current distribution across the gate width, thereby maintaining power gain while achieving high drive current through multiple fingers.
Data Source
AI summary
An apparatus includes an amplifier circuit including a first transistor and a second transistor. The first transistor may include a gate having a gate oxide with a first thickness and a first gate length. The second transistor may include a gate having a gate oxide with a second thickness and a second gate length. The first transistor and the second transistor may be connected in a cascode configuration and the second thickness and the second gate length are greater than the first thickness and the first gate length, respectively.