Cascode GaN SiC Power Device Gate Loss Reduction

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Solution Overview

Problem

High-frequency and high-power applications require faster switching devices with low conduction losses, which is difficult to achieve with silicon MOSFETs, and wide bandgap power devices like GaN and SiC face challenges such as high gate loss and complex gate driver designs, especially at high frequencies.

Innovation Solution

A cascode arrangement of a normally-on high-voltage SiC FET and a normally-off low-voltage GaN FET is used, with the GaN FET driving the SiC FET to optimize power loss, minimizing impedance-based parasitics and using epitaxial growth of GaN on SiC to reduce gate loss, resulting in a cascode GaN/SiC power device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If GaN HEMTs are used for high-frequency applications, then switching speed is improved, but output capacitance losses increase significantly

Engineering Contradiction:
Improveswitching speedVSAvoidoutput capacitance losses
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent introduces an intermediary device (SiC MOSFET or SiC JFET) between the gate driver and the GaN HEMT to mediate the switching process. This intermediary device absorbs the output capacitance discharge current, preventing it from flowing through the GaN HEMT and causing losses. The intermediary device acts as a buffer that handles the high-frequency switching transients while the GaN HEMT operates in a more controlled manner.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If SiC devices are used for high-voltage applications, then voltage rating is improved, but gate charge increases leading to higher gate loss

Engineering Contradiction:
Improvevoltage ratingVSAvoidgate loss
Core Design Contradiction:
StrengthVSLoss of energy

Solution Approach 1:

The patent segments the gate drive function by using two separate devices: a SiC device for high-voltage blocking and a GaN device for efficient gate driving. The SiC MOSFET/JFET handles the high-voltage switching with its superior breakdown characteristics, while the GaN HEMT provides the fast switching and low gate charge required for efficient operation. This segmentation allows each device to operate in its optimal performance region.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If lateral GaN HEMT structure is used, then manufacturing is simplified, but maximum electric field is limited by surface dielectric strength

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidmaximum electric field
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The patent employs a composite device structure combining SiC and GaN materials, each contributing their superior properties. The SiC layer provides high breakdown strength and thermal conductivity, while the GaN layer provides high electron mobility and low on-resistance. This composite heterostructure leverages the complementary strengths of both wide bandgap materials to achieve performance that neither material could provide alone.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cascode GaN/SiC device achieves reduced gate loss, simpler gate drive design, higher efficiency, and lower power consumption, suitable for high-frequency applications like wireless power transfer and radio-frequency plasma generation, with potential for increased power density.

Implementation Method 1

the second type of FET includes a gallium nitride (GaN) layer that is epitaxially grown on the silicon carbide (SiC) layer

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11101792B2Circuitry and methodology benefiting from reduced gate loss
Publication Date: 2021.08.24 THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIV
  • US11101792B2 patent drawing
  • US11101792B2 patent drawing
  • US11101792B2 patent drawing

AI summary

In specific examples, aspects are directed towards eliminating, mitigating or reducing gate loss in circuits including, for example, WBG power devices. One such example is directed towards an apparatus including first and second types of field-effect transistor (FET), where the first type is characterized as being a normally-on FET in a switching-circuit operation with a high-voltage rating, and the second type of FET is characterized as being a normally-off FET in a switching-circuit operation with a voltage rating that is much less than the high-voltage rating of the first type of FET circuit. The FET are arranged in a cascode manner so that, in response to a switching control signal received by the second type of FET circuit, the second type of FET circuit is active to drive the first type of FET.