Monolithic Cascode Multi-Channel HEMTs for High-Voltage Switching
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Solution Overview
Problem
Designing multi-channel high voltage transistors is challenging due to slow switching speeds in existing devices like IGBTs and SiC MOSFETs, and the complexity of nanometer-sized structures required for GaN devices, which complicates electric field management and voltage upscaling.
Innovation Solution
A monolithic cascode configuration of a low voltage E-mode transistor and a high voltage D-mode transistor is used, where the gate of the high voltage D-mode transistor is controlled by the low voltage E-mode transistor, utilizing a gallium nitride layer over a buffer layer with alternating AlGaN/GaN heterostructures to create two-dimensional carrier channels for improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If depletion-mode (D-mode) HEMTs are used for high voltage operation, then breakdown voltage (BV) is improved, but specific on-resistance (Rory) increases
Solution Approach 1:
The transistor is segmented into two distinct modes: a depletion-mode HEMT for high voltage operation and an enhancement-mode transistor for low voltage operation. This segmentation allows each portion to optimize its characteristics for its specific operating range, with the D-mode providing high BV and the E-mode providing low Rory when activated
Solution Approach 2:
The device dynamically switches between depletion-mode and enhancement-mode operation based on the applied gate voltage. When the gate voltage exceeds the threshold voltage, the enhancement-mode channel forms and provides low on-resistance conduction path, while below threshold the depletion-mode operation maintains high breakdown voltage capability
2Ease of manufacture
If planar gates are used in multi-channel HEMTs, then manufacturing is simplified, but electric field management becomes complex
Solution Approach 1:
The invention changes the operational parameter of the gate by introducing threshold voltage control through enhancement-mode operation. This parameter change allows the gate to actively manage electric fields by forming controlled accumulation layers that can be turned on and off, simplifying electric field management while maintaining planar gate fabrication simplicity
3Reliability
If enhancement-mode transistor is added to control D-mode transistor, then device complexity increases, but specific on-resistance decreases
Solution Approach 1:
The invention merges the depletion-mode HEMT and enhancement-mode transistor into a single integrated device structure sharing common source and drain regions. This merging reduces the overall device complexity compared to separate devices while achieving low specific on-resistance through the E-mode channel when activated
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-resistance and enhances Baliga's figure of merit, allowing for efficient high voltage switching with reduced complexity in fabrication and improved electric field management.
Implementation Method 1
at least one two-dimensional carrier channel formed at an interface of an aluminum gallium nitride material and a gallium nitride material
Data Source
AI summary
This disclosure provides semiconductor device including a first transistor with a first gate terminal, a first source terminal, and the first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity. The semiconductor device also includes a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor, a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal, and a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal. The first transistor and the second transistor are fabricated on the same wafer or substrate.