Cascode Voltage Level Shift Circuit for Stable PSRR
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Solution Overview
Problem
Conventional voltage level shift circuits face challenges in maintaining consistent differences between input and output potentials and suffer from deteriorated power supply rejection ratio due to manufacturing inaccuracies and power supply fluctuations, especially at low frequencies.
Innovation Solution
The proposed solution involves a voltage level shift circuit design that includes source follower circuits and cascode circuits, where the bias voltage of each cascode circuit is controlled by a bias voltage signal from an unconnected source follower circuit, and the use of P-channel enhancement type MOS transistors and N-channel depletion type MOS transistors on a P-type substrate, forming a complementary bias voltage control mechanism to maintain accuracy and improve power supply rejection ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional source follower circuits are used as voltage level shift circuits, then the circuit structure is simple, but the power supply rejection ratio deteriorates due to channel length modulation effect and parasitic capacitance
Solution Approach 1:
A cascode circuit is introduced as an intermediary component between the source follower circuit and the power supply. The cascode circuit includes a first transistor connected between the power supply and the source follower, with its gate receiving a bias voltage signal. This intermediary structure shields the source follower from power supply fluctuations, improving the power supply rejection ratio while maintaining the simplicity of the source follower configuration.
2Adaptability or versatility
If multiple voltage level shift circuits are used to expand input voltage range, then the input voltage range is expanded, but manufacturing inaccuracies cause uneven accuracy in maintaining the same difference between input and output potentials
Solution Approach 1:
A bias voltage generation circuit is implemented that automatically adjusts the bias voltage signal based on the actual operating conditions of the voltage level shift circuits. The circuit monitors the potential differences and provides feedback to correct manufacturing variations, ensuring that all voltage level shift circuits maintain consistent accuracy despite manufacturing inaccuracies.
Solution Approach 2:
The bias voltage signal is designed to be dynamically adjustable rather than fixed. By changing the bias voltage parameter based on operating conditions and manufacturing variations, the circuit compensates for inaccuracies in individual transistors, ensuring uniform performance across multiple voltage level shift circuits.
Data Source
AI summary
Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M1) and an N-channel depletion type MOS transistor (M3); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M2) and an N-channel depletion type MOS transistor (M4). In the voltage lever shift circuit, a cascode circuit using an N-channel depletion type transistor (M5) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M6) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.