Cascode Level Shifter Layout for Hot-Carrier Aging Resilience
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Solution Overview
Problem
Conventional level shifters degrade under extreme operating conditions due to hot carrier injection, leading to performance failure within a year, as they are not designed to handle high supply voltages, low temperatures, and high signaling frequencies in newer manufacturing processes.
Innovation Solution
Incorporating a cascode configuration with high-voltage isolation and cascode transistors, along with low-voltage transistors, to isolate and reduce stress on high-voltage cascode transistors, thereby maintaining suitable voltage headroom for pulldown transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifter circuits are used in newer manufacturing processes (e.g., 22 nm process), then interoperability between voltage domains is achieved, but hot carrier injection degrades performance under extreme operating conditions (high supply voltage, low temperature, high signaling frequency)
Solution Approach 1:
The level shifter circuit is segmented into multiple transistor stages including cross-coupled transistors, isolation transistors, and cascode transistors. Each segment performs a specific function: cross-coupled transistors provide signal regeneration, isolation transistors protect against voltage spikes, and cascode transistors reduce hot carrier injection effects. This segmentation allows optimization of each part for reliability under extreme conditions.
Solution Approach 2:
Isolation transistors are introduced as intermediary elements between the input and output stages of the level shifter. These transistors act as mediators that block harmful voltage spikes and hot carriers from propagating through the circuit, thereby protecting the core functionality while maintaining signal integrity. The isolation transistors extend circuit lifetime by preventing cumulative damage from hot carrier injection.
2Reliability
If high supply voltage (e.g., 3.8 V) is used to ensure proper operation in high power domain, then signal translation capability is maintained, but hot carrier injection increases causing threshold voltage shift
Solution Approach 1:
The circuit design acknowledges that hot carrier injection is inevitable at high voltages but converts this harmful effect into a manageable parameter. By using cascode transistor configurations and proper biasing, the design ensures that threshold voltage shifts caused by hot carrier injection remain within acceptable limits (<15 mV after 10 years), thereby maintaining signal translation capability while operating at high supply voltages.
Solution Approach 2:
The circuit employs parameter optimization including transistor sizing, bias voltage selection, and doping profiles to minimize hot carrier injection effects. By carefully selecting transistor dimensions and bias conditions, the design maintains proper signal translation at high supply voltages while reducing the magnitude of threshold voltage shifts caused by hot carrier injection.
3Productivity
If cross-coupled transistors are used for signal regeneration, then signaling frequency response is improved, but voltage headroom requirements increase causing performance degradation
Solution Approach 1:
The circuit uses parameter optimization including low-voltage transistor designs and adjusted biasing schemes to reduce voltage headroom requirements. By modifying transistor characteristics and operating points, the design maintains high signaling frequency performance while reducing the voltage overhead needed for proper operation, making the level shifter suitable for low-voltage domains.
Data Source
AI summary
An aging resilient level shifter has an increased lifetime as compared to a conventional level shifter. In at least one embodiment, a method for level-shifting a received signal from a first voltage domain to a second voltage domain includes controlling a cross-coupled pair of transistors according to an input signal and a complementary input signal to generate a signal on a pair of complementary nodes. The cross-coupled pair of transistors has a first doping type and the controlling uses a pair of transistors having a second doping type. The second doping type is complementary to the first doping type. The method includes isolating the pair of transistors from the pair of complementary nodes using a pair of isolation transistors and a pair of cascode transistors. The pair of cascode transistors is coupled between the pair of transistors and the pair of complementary nodes.