Cascode RF Amplifier Gate Capacitor Layout for Balanced Gain
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Solution Overview
Problem
The high-frequency amplifier disclosed in Patent Literature 1 experiences an imbalance in the amplification operations of its gate fingers due to differing parasitic components, leading to increased combined loss of high-frequency signals and decreased output power.
Innovation Solution
The high-frequency amplifier is configured such that capacitors are arranged to ensure equal impedances are obtained when looking toward the capacitors from each gate finger of the common-gate transistor, thereby reducing the imbalance between the amplification operations of the gate fingers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If capacitors are connected to the gate bus bar in a conventional high-frequency amplifier, then the drain voltage can be doubled compared to a single common-source FET amplifier, but the distances from the gate fingers to the capacitor differ causing unequal parasitic components and imbalance in amplification operations
Solution Approach 1:
The single capacitor is divided into multiple capacitors, with each capacitor connected to a corresponding gate finger. This segmentation ensures that each gate finger has an equal distance to its associated capacitor, creating equal parasitic components and balanced amplification operations across all gate fingers while maintaining the voltage doubling effect.
2Stress or pressure
If the capacitance value of the capacitor is appropriately set, then the voltage applied to the drain of the common-source FET can be twice as high, but the unequal distances to the capacitor cause different parasitic components between gate fingers
Solution Approach 1:
Each gate finger is assigned a dedicated capacitor positioned at an equal distance from that specific gate finger. This local quality approach ensures that the parasitic components are uniform for each gate finger individually, while the overall system maintains high drain voltage capability through the parallel capacitor configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the imbalance between the amplification operations of the gate fingers, resulting in reduced combined loss of high-frequency signals and increased output power, capable of applying a drain voltage twice that of a single common-source FET amplifier.
Implementation Method 1
a capacitor having a first end connected to the gate bus bar and a second end grounded
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A high-frequency amplifier (1) includes a common-source transistor (12) that has gate fingers (14-1 to 14-8), drain fingers (15-1 to 15-4), and source fingers (16-1 to 16-5), amplifies a signal applied to each (14-m; m=1, 2,..., 8) of the gate fingers as a signal to be amplified, and outputs an amplified signal from each (15-j; j=1, 2, 3, and 4) of the drain fingers, and a common-gate transistor (32) that has source fingers (33-1 to 33-8) connected to the drain fingers (15-1 to 15-4) of the common-source transistor (12), drain fingers (34-1 to 34-4), and gate fingers (35-1 to 35-8), and amplifies the amplified signal output from each (15-j) of the drain fingers of the common-source transistor (12). The high-frequency amplifier (1) also includes a gate bus bar (38) connected to the gate fingers (35-1 to 35-8) of the common-gate transistor (32), and capacitors (39-1 to 39-8) each having a first end connected to the gate bus bar (38) and a second end grounded. The high-frequency amplifier (1) is configured in such a way that the capacitors (39-1 to 39-8) are arranged at respective positions where impedances obtained by looking toward the respective capacitors (39) from the respective gate fingers (35-m) of the common-gate transistor (32) are equal to each other.