Cascode Circuit Voltage Clamping for Avalanche Breakdown Control
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Solution Overview
Problem
High voltage devices with low voltage FETs face reliability issues due to excess voltage conditions, such as leakage differences and switching speed mismatches, leading to operation and manufacturing challenges in cascode circuits.
Innovation Solution
The implementation of a cascode circuit with enhanced capacitance and avalanche breakdown control using semiconductor structures with doped regions and conductive trenches, which provide capacitance and voltage clamping to restrict voltage levels at the source and drain of transistors, mitigating avalanche breakdown and ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode arrangement with a low voltage FET coupled to a high voltage device is used to provide controlling gate voltage, then the device can operate as normally off with high voltage capability, but excess voltage can occur that harms either or both of the high voltage device and the low voltage FET
Solution Approach 1:
The patent introduces a cascode structure with a low voltage FET as an intermediary device between the control circuit and the high voltage device. This intermediary FET acts as a buffer that protects the high voltage device from excess voltage conditions while enabling reliable normally-off operation. The low voltage FET absorbs voltage stress and prevents direct exposure of the high voltage device to harmful voltage transients.
Solution Approach 2:
The patent implements protective circuitry including clamp diodes and capacitance elements that are pre-configured to cushion against voltage transients before they can damage the devices. The capacitance coupled between the drain of the low voltage FET and source of the high voltage device provides beforehand cushioning by absorbing voltage spikes and preventing avalanche breakdown during switching transitions.
2Speed
If the low voltage FET switches off faster than the high voltage device, then switching speed is improved, but operation and reliability issues arise due to voltage mismatches
Solution Approach 1:
The patent places capacitance elements in advance between the drain of the low voltage FET and the source of the high voltage device to cushion against voltage transients that occur when the low voltage FET switches off faster than the high voltage device. This beforehand cushioning prevents reliability issues by absorbing the voltage mismatch energy before it can cause damage.
Solution Approach 2:
The cascode structure provides inherent feedback mechanisms where the voltage at the drain of the low voltage FET (which is connected to the gate of the high voltage device) automatically adjusts the gate voltage based on the switching state. This feedback ensures that even when switching speeds differ, the high voltage device responds appropriately without causing reliability issues.
3Object-affected harmful factors
If capacitance is added to the cascode circuit to mitigate voltage transients, then voltage clamping is improved, but device complexity increases
Solution Approach 1:
The patent merges the capacitance function directly into the cascode circuit structure by coupling capacitance between the drain of the low voltage FET and the source of the high voltage device. This merging combines the voltage clamping function with the existing switching architecture, avoiding the need for separate protective circuits and thereby minimizing the increase in device complexity while still providing effective transient mitigation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of high voltage devices by providing additional capacitance and voltage clamping, preventing overvoltage conditions and improving long-term reliability and efficiency in switching applications.
Implementation Method 1
The conductive trenches are configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor
Implementation Method 2
mitigate avalanche breakdown of the second transistor by restricting voltage at one of the source and the drain of the second transistor
Data Source
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AI summary
Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.