Cascoded NMOS Voltage Regulator for Flash Memory Compatibility
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Solution Overview
Problem
Conventional voltage regulators that use high voltage devices are not compatible with certain integrated circuits, such as those requiring on-chip flash memory, and are expensive when off-chip flash memory is used, while low voltage devices are compatible with flash memory technology but pose challenges in regulating high voltage sources like USB's Vbus, which can range from 5V to 20V.
Innovation Solution
A voltage regulator circuit implemented with low voltage devices, specifically cascoded NMOS transistors, using a resistor network and charge pump to regulate high voltage sources down to low voltage outputs, ensuring the low voltage devices do not exceed their breakdown voltage limits, with leakage current kept below 1 uA and power efficiency improved by avoiding high voltage charge pumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage devices are used to regulate Vbus, then the charging voltage can be regulated, but the device is not compatible with flash memory technology and is expensive
Solution Approach 1:
The voltage regulation function is divided into two independent modules: a high voltage module (first transistor) that handles the high voltage input without breaking down, and a low voltage module (second transistor) that provides the regulated output compatible with flash memory. This segmentation allows each module to be optimized for its specific voltage range, achieving both voltage regulation capability and flash memory compatibility.
2Ease of manufacture
If low voltage devices are used to regulate high voltage, then the device is compatible with flash memory technology, but the devices may exceed their breakdown voltage limits
Solution Approach 1:
The first high voltage transistor acts as an intermediary between the high voltage source and the low voltage transistor. It steps down the high voltage to a safe level before it reaches the second low voltage transistor, protecting the flash memory-compatible device from exceeding its breakdown voltage limits while maintaining compatibility with flash memory technology.
3Reliability
If conventional voltage regulator circuits are used, then voltage regulation is achieved, but leakage current is high and power efficiency is low
Solution Approach 1:
The circuit uses different transistor parameters (threshold voltages, channel widths, lengths) optimized for their respective voltage ranges. The first transistor is designed with parameters suitable for high voltage operation, while the second transistor uses parameters optimized for low voltage regulation. This parameter optimization minimizes leakage current in both stages, improving overall power efficiency while maintaining voltage regulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low leakage, low power consumption, and low area utilization while effectively regulating high voltage sources to low voltage outputs, compatible with flash memory technology, and suitable for various voltage ranges, ensuring the safety and efficiency of low voltage devices.
Implementation Method 1
A multi-stage charge pump has an output connected to a gate electrode of the first NMOS transistor, the multi-stage charge pump configured to generate a bias voltage at the output, the bias voltage greater than a device threshold voltage
Data Source
AI summary
Embodiments are provided for voltage regulators that include a first, a second, a third, and a fourth NMOS transistor cascoded between a high voltage source and a low voltage output; a resistor network including a first, a second, a third, and a fourth resistor connected in series between the high voltage source and ground, wherein gate electrodes of the second, third, and fourth NMOS are respectively connected to nodes between the first and second resistors, the second and third resistors, and the third and fourth resistors; and a multi-stage charge pump configured to provide a first bias voltage to a gate electrode of the first NMOS and a second bias voltage to the gate electrode of the second NMOS.