Apparatus Without Intermediate Ac Conversion TRIZ Cases

A charge pump circuit uses capacitors to transfer energy to a switch node coupled via an inductor.

A modulated reference voltage circuit switches between two values to enable earlier charge pump switching.

A DC converter filter module integrates input and output inductors on a single magnetic core to suppress common mode interference.

A regulated charge pump circuit uses level shifters and a voltage follower to generate an accurate output voltage.

A voltage regulator generates d-axis and q-axis reference currents with a 90-degree phase difference to mitigate second-order harmonics.

A self-sustaining power supply uses charge pump mechanisms to generate internal control signals for high voltage clamping.

Cascaded boosting modules multiply voltage conversion ratios while reducing power loss compared to traditional topologies.

A voltage generation circuit adjusts driving voltages to maintain stable internal levels.

Precharged capacitor networks translate signals between voltage tiers, eliminating complex level shifter arrays and reducing power consumption.

A voltage reference circuit uses a current mirror function to generate stable base-emitter voltages for low power supply operation.

A switched-capacitor regulator system adjusts switching frequency to optimize efficiency during high-speed battery charging.

A cascoded NMOS voltage regulator circuit uses a resistor network and charge pump to step down high voltage inputs.

Pre-charging flying capacitors via dedicated current sources eliminates inrush currents during startup, protecting switching transistors from damage.

A power supply device adjusts output voltage based on detected load current to maintain stable applied voltage at the terminals.

Synchronizing the boost circuit with the frame signal maintains stable voltage while reducing power dissipation in liquid crystal displays.

A voltage regulator uses dynamic mode switching to maintain stable output voltage across varying load conditions.

A charge pump circuit uses self-timed switching to generate a stable supply voltage.

A charge pump circuit dynamically adjusts output voltage levels using capacitor switching configurations to match power requirements.

A charge pump adjusts output voltage by reconfiguring package substrate wiring.

A shared inductor and charge pump generate two supply voltages for subscriber line interface circuits, reducing power consumption.

A Type III error amplifier uses an assist circuit to rapidly charge or discharge a compensation capacitor for faster transient response.

A boosting circuit uses detection and control circuits to manage pre-charging phases for stable voltage output.

A dual-loop regulated switched capacitor converter circuit uses a digital controller and pulse modulator to adjust switch sizes and clock frequency.

Polysilicon diodes shunt leakage current to prevent transistor breakdown during power-down.

Gate driving circuit adjusts switching transistor duty cycle to suppress steep output voltage changes and transient displacement during charge pump startup.

Auxiliary capacitor isolates charge pump current from sensing circuit to maintain regulation stability.

A quantum charge modulator dynamically adjusts switch signal frequency to maintain stable average operation across multiple cycles.

Parallel capacitor circuit reduces controller design effort and costs by merging independent controllers into a single unit for photovoltaic inverters.

A boosted circuit supplies a higher operation voltage to sensing elements within the power switch unit.

Dynamic threshold selection shifts regulator noise above 40 kHz, resolving the trade-off between high load handling capability and audible mechanical vibration.

A bi-directional DC/DC converter topology uses inductors and active switches to transfer power between bipolar circuits.

A two-stage NMOS charge pump circuit enhances charge pumping efficiency using auxiliary capacitors and complementary clock signals.

A negative charge pump uses a leaky circuit device to drain positive charges from the output node.

A multi-level DC-to-DC converter circuit uses a parallel shadow capacitor balancing mechanism to manage voltage distribution across internal components.

Dynamic commutation timing reduces chip area and electromagnetic interference while maintaining output voltage accuracy.

A drive circuit controls output node impedance using dual clock signals to generate stable drive clocks.

Dedicated precharge paths bypass switching resistance to eliminate voltage drop and improve current efficiency in multi-stage charge pump circuits.

Segmented polysilicon and metal plate capacitors boost voltage from 5.5 V to 40 V while reducing die area and capacitor stress.

Dual charge pump circuit adjusts current levels to stabilize negative voltage output, reducing start-up time and power consumption.

A hybrid DC-DC converter merges buck, switched capacitor, and isolation stages into a single switching structure.

A capacitor cross-coupled 2-phase buck converter topology uses flying capacitors to maintain constant phase voltage and limit inductor stress.

A voltage scaling-up circuit selects a higher magnitude voltage to bias PMOS transistor bulks during power-on.

A reconfigurable Buck-Boost DC-DC converter architecture merges a linear regulator and switched-capacitor stage using a shared capacitor array.

Shifted clock signals in a multi-stage charge pump eliminate series-connected capacitors, reducing circuit complexity and chip area.

Cascaded MOS switching stages with feedback regulation reduce current consumption by minimizing leakage currents in high voltage generation.

A power converter uses a flying capacitor and inductor network to reduce RMS input current.

Sequential switching order prevents parasitic bipolar transistor turn-on caused by stray inductance, reducing peak voltage ringing across flying capacitors.

A dual-phase hybrid DC-DC converter uses inductors to charge flying capacitors, reducing component volume.

A charge pump system transitions between operational modes to reduce static and dynamic power consumption.