Multi-stage Charge Pump with Shifted Clock Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuit designs require higher voltages than the available supply voltages, leading to complex and area-intensive multi-stage charge pumps that necessitate series-connected capacitors and internal biasing, increasing complexity and chip area consumption.
Innovation Solution
A multi-stage charge pump design where downstream stages are controlled by shifted clock signals, eliminating the need for series-connected or high voltage capacitors, reducing complexity and chip area while improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If series-connected capacitors are used in downstream stages of multi-stage charge pumps, then higher output voltages can be generated, but circuit complexity and chip area consumption increase
Solution Approach 1:
The patent changes the voltage level parameter of clock signals in downstream stages by applying voltage shifting circuits. The clock signals are shifted to higher voltage levels matching the stage's operating voltage, allowing capacitors to operate at lower voltages while still achieving the required output voltage through the charge pumping action. This eliminates the need for series-connected high-voltage capacitors.
2Power
If series-connected capacitors are used in downstream stages of multi-stage charge pumps, then higher output voltages can be generated, but chip area consumption increases
Solution Approach 1:
The patent transforms the voltage parameter of clock signals using shifting circuits in downstream stages. This allows the use of low-voltage capacitors instead of high-voltage capacitors, significantly reducing the chip area required for capacitor implementation while maintaining the ability to generate high output voltages through multi-stage charge pumping.
3Power
If high voltage capacitors are used in downstream stages, then higher output voltages can be generated, but reliability decreases
Solution Approach 1:
The patent applies voltage shifting to clock signals in downstream stages, transforming them to match the stage's voltage level. This enables the use of low-voltage capacitors with higher reliability characteristics instead of high-voltage capacitors, while still achieving the required high output voltage through the charge pump mechanism.
4Ease of manufacture
If internal capacitor node biasing is implemented, then series-connected capacitors can function properly, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex internal capacitor node biasing circuitry from downstream stages. By using voltage-shifted clock signals that naturally provide the required voltage levels, the need for separate biasing circuits is eliminated, simplifying the overall device architecture while maintaining proper capacitor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces circuit complexity and chip area consumption while enhancing reliability by using shifted clock signals to generate higher output voltages without the need for series-connected capacitors, allowing for efficient generation of high positive and negative voltages.
Implementation Method 1
The clock signal shift circuit can be configured to output a second clock signal, which has second high and low states that are different from the first high and low states, in response to the input voltage and the first clock signal
Implementation Method 2
a multi-stage positive charge pump is used to generate relatively high positive voltages and, particularly, positive voltages that are greater than Vdd
Data Source
AI summary
Disclosed is a multi-stage charge pump. A first stage is controlled by a first clock signal. A second stage is controlled by a second clock signal, which has high and low states that are shifted relative to the high and low states of the first clock signal. The high and low states of the second clock signal can be higher than the high and low states, respectively, of the first clock signal for a positive charge pump and vice versa for a negative charge pump. Any additional stage is similarly controlled by an additional clock signal that is shifted with respect to the clock signal controlling the immediately preceding stage. By shifting the high and low states of clock signals controlling downstream stages, the need for series-connected or high voltage capacitors in the downstream stages is eliminated and circuit complexity and area consumption are reduced.