Negative Charge Pump With Leaky Circuit Device
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Solution Overview
Problem
Conventional charge pumps have limited response times due to the rate of capacitor charging and discharging, and their timing circuitry is complex and area-intensive, requiring substantial semiconductor substrate space.
Innovation Solution
An improved negative charge pump design with a leaky circuit device and a two-clock charge pump stage configuration that includes pass transistors and capacitors, along with a four-phase clock circuit, enhances pumping speed by preventing positive charge accumulation and using phased clock signals to efficiently charge and discharge capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional charge pump design is used, then the circuit structure is simple, but the response time is limited by capacitor charging and discharging rate
Solution Approach 1:
The charge pump is divided into multiple stages, each with its own capacitor and switching network. This segmentation allows independent optimization of each stage's charging/discharging rate, thereby improving overall response time without requiring a complete redesign of the entire circuit structure
Solution Approach 2:
The patent employs periodic switching of capacitors between charging and discharging states using clock signals. This periodic action enables the capacitors to be fully charged and discharged at optimized intervals, increasing the pumping speed while maintaining a manageable circuit structure through rhythmic operation
2Area of stationary object
If conventional timing circuitry is used, then the charge pump operation is controllable, but the timing circuitry requires substantial area on semiconductor substrate
Solution Approach 1:
The timing circuitry is merged with the charge pump stages themselves, where the same switching network that controls capacitor charging also generates the timing signals. This integration eliminates separate timing circuit blocks, reducing substrate area while maintaining operational control through the unified switching mechanism
Solution Approach 2:
The clock signals and switching networks serve multiple functions: they control capacitor charging/discharging, generate timing references, and coordinate stage operations. This multi-functionality allows a single circuit element to perform several roles, reducing the overall area required for timing control while preserving full operational capability
3Productivity
If capacitor charging and discharging rate is increased, then pumping speed improves, but the circuit complexity and area requirements increase
Solution Approach 1:
The patent implements overlapping charging and discharging cycles across multiple stages, where while one capacitor is charging, another is discharging. This continuity ensures that charge transfer never stops, maintaining high pumping speed while allowing each individual capacitor to operate at moderate, manageable rates without requiring overly complex high-speed switching circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved charge pump achieves a 20-30% increase in pumping speed compared to conventional charge pumps, with faster voltage generation and reduced complexity and area requirements.
Implementation Method 1
the rate at which the capacitors of the charge pump are charged and discharged
Implementation Method 2
circuit element for reducing a positive voltage build-up in the at least one stage
Data Source
AI summary
A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.