Voltage Scaling-Up Circuit Bulk Biasing for PMOS Leakage
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Solution Overview
Problem
Prior art cross-coupled charge pumps face issues with prolonged settling time and potential leakage current due to delayed bulk biasing of PMOS transistors and large external capacitors, which hinder system startup and introduce undesired currents.
Innovation Solution
A voltage scaling-up circuit incorporating a charge pump circuit and a multiplexer circuit that automatically biases the bulk of PMOS transistors to a higher voltage level by selecting the higher magnitude between a predetermined voltage and a pumped voltage, reducing settling time and preventing reverse currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the bulk of PMOS transistors is biased at the output voltage during power-on start-up, then the circuit structure is simple, but the settling time is prolonged and leakage current occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging the bulk of PMOS transistors to a higher voltage level (e.g., VDD) before the output voltage reaches that level. This is achieved through a dedicated bulk biasing circuit that proactively establishes the correct bulk voltage during power-on, preventing the reverse bias condition before it can cause leakage or delay settling.
Solution Approach 2:
The patent introduces an intermediary bulk biasing circuit that mediates between the power supply and the PMOS transistor bulks. This intermediary circuit actively manages the bulk voltage independently from the output voltage, using components like capacitors and transistors to ensure the bulk is always at the appropriate higher voltage level, thus decoupling the bulk biasing from the output voltage ramping.
2Stability of the object's composition
If a large external capacitor is used at the output, then the output voltage stability is improved, but the charging time from 0V to target voltage is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-charging the bulk of PMOS transistors to a higher voltage level (e.g., VDD) before the output voltage reaches that level. This is achieved through a dedicated bulk biasing circuit that proactively establishes the correct bulk voltage during power-on, preventing the reverse bias condition before it can cause leakage or delay settling.
Solution Approach 2:
The patent introduces an intermediary bulk biasing circuit that mediates between the power supply and the PMOS transistor bulks. This intermediary circuit actively manages the bulk voltage independently from the output voltage, using components like capacitors and transistors to ensure the bulk is always at the appropriate higher voltage level, thus decoupling the bulk biasing from the output voltage ramping.
3Reliability
If the output voltage ramps slowly to target voltage, then the capacitor charging is complete, but reverse leakage current flows to the charge pump
Solution Approach 1:
The patent applies preliminary action by pre-charging the bulk of PMOS transistors to a higher voltage level (e.g., VDD) before the output voltage reaches that level. This is achieved through a dedicated bulk biasing circuit that proactively establishes the correct bulk voltage during power-on, preventing the reverse bias condition before it can cause leakage or delay settling.
Solution Approach 2:
The patent introduces an intermediary bulk biasing circuit that mediates between the power supply and the PMOS transistor bulks. This intermediary circuit actively manages the bulk voltage independently from the output voltage, using components like capacitors and transistors to ensure the bulk is always at the appropriate higher voltage level, thus decoupling the bulk biasing from the output voltage ramping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly shortens the ramping up time of the output voltage, mitigates leakage currents, and prevents reverse currents from flowing back to the charge pump circuit, enhancing power-on speed and efficiency.
Implementation Method 1
charges are periodically pumped through the NMOS transistors M1 and M2 to pumping nodes PN1 and PN2 at which the voltages VPN1 and VPN2 can be higher than the input voltage VDD
Implementation Method 2
a multiplexer circuit, configured to operably select one of a predetermined voltage and the pumped voltage which has a higher magnitude as a scaled output voltage
Implementation Method 3
there could be a current flowing from the input voltage to the bulk of the PMOS transistors when the output voltage VOUT is below a voltage level of (VDD-Vthp)
Data Source
AI summary
The present invention provides a voltage scaling-up circuit which comprises a charge pump circuit and a multiplexer circuit. The charge pump circuit which includes at least one pumping switch, and is configured to operably periodically converts an input voltage to a pumped voltage onto a pump output node through the at least one pumping switch by charging and pumping, such that the pumped voltage has a scaling factor over the input voltage, wherein the at least one pumping switch has a bulk. The multiplexer circuit senses a predetermined voltage and the pumped voltage and selects one of the predetermined voltage and the pumped voltage which has a higher magnitude as a scaled output voltage at a scaled output node; wherein the bulk of the at least one pumping switch is biased to the scaled output voltage.