NMOS Charge Pump Circuit Alleviates Body Effect

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Solution Overview

Problem

Classic Dickson charge pump circuits suffer from the body effect, which degrades charge transfer efficiency due to substrate effects, especially in later stages, and existing solutions either increase fabrication complexity or introduce parasitic bipolar effects.

Innovation Solution

A two-stage NMOS charge pump circuit with four NMOS transistors and auxiliary capacitors driven by two-phase complementary clock signals, which alleviates the body effect by using NMOS transistors constructed directly on a p-type substrate without deep n-well isolation, simplifying the clock generation and reducing parasitic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If NMOS transistors are isolated in deep n-well to alleviate body effect, then charge transfer efficiency is improved, but fabrication complexity increases

Engineering Contradiction:
Improvecharge transfer efficiencyVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the substrate connection parameter from ground to a separately biased substrate terminal, allowing independent voltage control. This parameter change enables the NMOS transistors to operate without body effect degradation while maintaining simple planar fabrication, resolving the contradiction between efficiency improvement and fabrication complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediate substrate bias voltage as a mediator between the ground and the NMOS substrates. This intermediate voltage level compensates for the body effect without requiring deep n-well isolation structures, achieving high charge transfer efficiency while keeping the fabrication process simple

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If deep n-well isolation is used to reduce body effect, then charge pumping efficiency is improved, but parasitic bipolar effects are introduced

Engineering Contradiction:
Improvecharge pumping efficiencyVSAvoidparasitic bipolar effect
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the electrical parameter of the substrate from grounded to independently biased, which eliminates the need for deep n-well isolation structures. This parameter change simultaneously improves charge pumping efficiency by reducing body effect and eliminates parasitic bipolar effects that would be introduced by deep n-well configurations

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If NMOS transistors are connected to ground substrate, then fabrication is simplified, but body effect degrades threshold voltage

Engineering Contradiction:
Improvefabrication simplicityVSAvoidthreshold voltage stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an intermediary substrate bias voltage that acts as a mediator between ground and the NMOS substrates. This intermediary voltage compensates for the body effect and stabilizes the threshold voltage while maintaining the simple planar fabrication structure with direct substrate connection, thus resolving the contradiction between fabrication simplicity and threshold voltage stability

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances charge pumping efficiency, reduces fabrication complexity, and maintains high voltage output at low supply voltages, suitable for low power consumption in handheld devices, while minimizing silicon area and power consumption.

Implementation Method 1

charge transfer efficiency is greatly reduced

Methodology Applied
Scientific EffectCharge transfer:

Implementation Method 2

Each stage of the charge pump is formed by a diode or a diode-like device plus a capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

A two-stage NMOS charge pump circuit with four NMOS transistors and auxiliary capacitors driven by two-phase complementary clock signals

Methodology Applied
Scientific EffectTwo-phase clock signaling:

Data Source

PatentUS9509213B1Charge pump circuit suitable for low voltage operation
Publication Date: 2016.11.29 GIANTEC SEMICON LTD INC
  • US9509213B1 patent drawing
  • US9509213B1 patent drawing
  • US9509213B1 patent drawing

AI summary

A charge pump device with NMOS transistor circuit is provided for low voltage operation. The charge pump stage, comprising four NMOS transistors and three capacitors, is configured to alleviate the substrate body effect and the charge transfer loss. The charge pump circuit can be constructed on a p-type semiconductor substrate directly without deep N well isolation. The circuit is driven by two non-overlapping complementary clock signals, which can be generated easily with an integrated fabrication. The charge pump device can be implemented with a multiple stage to provide a stable high voltage output.