Cavity Cover Layer Structure for Optoelectronic Chip Isolation
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Solution Overview
Problem
Optoelectronic components, such as displays, face challenges in achieving compactness, improved beam shaping, and stability against electrical short circuits due to cavity depths that are not optimized for semiconductor chip placement and wiring, leading to potential short circuits and complex manufacturing processes.
Innovation Solution
A component design featuring a carrier, semiconductor chip, and a cover layer with varying vertical height, incorporating an intermediate electrically insulating layer that extends into cavities to facilitate chip placement and wiring, while allowing for deeper cavities and independent reflective materials on cavity walls to enhance beam shaping and reduce short circuit risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If deeper cavities are used to improve forward emission and beam shaping, then beam shaping properties are improved, but chip placement and wiring become more difficult due to larger topographical differences
Solution Approach 1:
The cavity is formed in the cover layer before the semiconductor chip is attached to the carrier. This preliminary formation of the cavity allows for deeper structures without interfering with subsequent chip placement operations, as the chip is mounted on a flat carrier surface and the cavity is created afterward to accommodate the chip and enable improved light extraction and beam shaping.
Solution Approach 2:
The cavity extends in the vertical dimension (depth) while the chip placement occurs on the horizontal plane (carrier surface). By separating the placement operation (2D surface operation) from the cavity structure (3D vertical feature), the patent resolves the topographical conflict - the chip sits on a flat surface for easy placement, while the cavity provides the needed vertical depth for optical performance.
2Reliability
If metal layers are applied to cavity side walls for electrical contacting, then electrical contact is achieved, but the risk of short circuits increases during wiring and operation
Solution Approach 1:
An intermediate layer is introduced between the metal layer on the cavity side wall and the semiconductor chip. This intermediate layer acts as a mediator that provides electrical contact functionality while preventing direct contact between conductive elements, thereby eliminating the short circuit risk. The intermediate layer allows the system to maintain both electrical connectivity and safety.
Solution Approach 2:
The harmful short circuit risk is extracted and isolated by introducing the intermediate layer that separates conductive paths. The metal layer retains its electrical contact function while the intermediate layer removes the harmful interaction (short circuit possibility) between adjacent conductive elements.
3Ease of manufacture
If cavities are formed before semiconductor chip attachment to enable side wall metal layer application, then manufacturing process is simplified, but cavity depth must be limited to barely larger than chip height
Solution Approach 1:
The cavity is formed in the cover layer before the semiconductor chip is attached to the carrier. This preliminary formation of the cavity allows for deeper structures without interfering with subsequent chip placement operations, as the chip is mounted on a flat carrier surface and the cavity is created afterward to accommodate the chip and enable improved light extraction and beam shaping.
Data Source
AI summary
A component includes a carrier, at least one semiconductor chip, an intermediate layer and a cover layer. The semiconductor chip, the intermediate layer and the cover layer are arranged on the carrier. The cover layer has at least one cavity wherein the semiconductor chip is arranged. The intermediate layer is electrically insulating and is arranged in regions along the vertical direction between the carrier and the cover layer. The intermediate layer extends along lateral direction into the cavity and adjoins the semiconductor chip. The cover layer has a vertical height that varies depending on the lateral positions of the cover layer and has a reduced vertical height at the positions of the intermediate layer.