Cavity Semiconductor Package Layout for Thinner 3D Die Integration
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in efficiently arranging and connecting semiconductor dies to achieve optimal electrical performance and reduced package thickness, particularly in 3D packaging and 3DIC devices, while maintaining reliability and yield.
Innovation Solution
A manufacturing method involving a redistribution layer with multiple dielectric and metallization layers, followed by die placement, molding, and dicing, with a cavity formation in the circuit substrate to accommodate dies, and underfilling to enhance electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If semiconductor dies are arranged in traditional 2D packaging, then manufacturing simplicity is maintained, but package thickness is increased and electrical performance is degraded
Solution Approach 1:
The patent transitions from traditional 2D packaging arrangement to 3D packaging by forming a cavity in the circuit substrate and placing the semiconductor die within this cavity. This dimensional change allows the die to be positioned at different heights and orientations, reducing the overall package thickness while improving electrical performance through shorter interconnect paths.
Solution Approach 2:
The semiconductor die is nested within the cavity formed in the circuit substrate, creating a compact structure where the die is embedded rather than surface-mounted. This nesting approach maximizes space utilization and reduces the package footprint and thickness.
2Reliability
If cavity formation is implemented to reduce package thickness, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The cavity is formed in the circuit substrate before the semiconductor die is placed and bonded to the redistribution layer. This preliminary cavity formation allows for optimized die positioning and shorter interconnect paths, improving electrical performance while enabling subsequent standard bonding and molding processes.
Solution Approach 2:
The cavity acts as an intermediary structure that facilitates better electrical connection between the semiconductor die and the circuit substrate. By providing a recessed mounting position, the cavity reduces the length of interconnect paths and improves signal integrity without requiring complex direct bonding techniques.
3Reliability
If underfill is applied to enhance structural integrity, then reliability is improved, but manufacturing time and complexity increase
Solution Approach 1:
The underfill material is applied to automatically fill the gap between the semiconductor die and the circuit substrate through capillary action. This self-leveling property eliminates the need for precise dispensing control and automatic removes voids, improving structural integrity while maintaining manufacturing efficiency through a simple, self-correcting process.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.