Cavity Semiconductor Package With Floating Metal Plate Interconnects
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in efficiently arranging and connecting semiconductor dies within a package to optimize size and electrical connectivity, particularly in three-dimensional integrated circuits (3DICs), leading to inefficiencies in space utilization and electrical performance.
Innovation Solution
A manufacturing method involving a redistribution layer with alternating dielectric and metallization layers, followed by die placement, encapsulation, and connection to a circuit substrate with a cavity design that accommodates dies, using underfills and conductive elements to enhance electrical connectivity and reduce package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If semiconductor dies are arranged in conventional packaging configurations, then electrical connectivity is achieved, but package size and thickness are increased
Solution Approach 1:
The patent transitions from conventional two-dimensional die arrangement to a three-dimensional configuration where dies are placed on both the front and back surfaces of the substrate. This dimensional change allows electrical connections to be made through the substrate thickness, significantly reducing package thickness while maintaining connectivity through vertical interconnections.
Solution Approach 2:
The patent embeds conductive elements and interconnection structures within the substrate itself, creating nested layers of electrical pathways. The conductive traces are embedded within the substrate material, with connection pads on both surfaces, allowing compact integration of interconnection functionality within the package structure.
2Area of stationary object
If semiconductor dies are arranged to optimize space utilization, then package size is reduced, but electrical performance and connectivity are degraded
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) to create vertical electrical pathways through conductive traces embedded in the substrate. This allows compact two-dimensional die arrangement while maintaining electrical performance through three-dimensional interconnection paths, effectively decoupling area optimization from electrical performance.
Solution Approach 2:
The substrate acts as an intermediary element that provides embedded conductive traces to bridge connection pads on opposite surfaces. This intermediary structure enables efficient electrical connectivity between dies arranged in compact configurations, overcoming the limitations of direct surface-mounted interconnections.
3Productivity
If conventional die arrangement methods are used, then manufacturing simplicity is maintained, but space utilization and electrical paths are inefficient
Solution Approach 1:
The conductive traces are pre-formed and embedded within the substrate before die attachment. This preliminary preparation of the interconnection structure simplifies the overall manufacturing process by eliminating the need for complex post-attachment routing and wiring, while enabling efficient space utilization through optimized trace layouts.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.