Charge Balanced Extended Drain NMOS for High Voltage ICs
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Solution Overview
Problem
Current methods for adding high voltage capability to integrated circuits are costly and inefficient, particularly due to the need for multiple gate dielectric thicknesses and increased series resistance in high power applications.
Innovation Solution
The development of charge balanced extended drain NMOS transistors with an n-type substrate source, which reduces capacitance and series resistance by fully depleting the extended drain region, allowing higher voltage to be dropped across a shorter length, thereby saving area and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If extended drain transistors are used to avoid two gate dielectric thicknesses, then manufacturing cost is reduced, but series resistance increases in high power applications
Solution Approach 1:
The patent applies local quality by creating an n-type substrate source with specific doping characteristics in a localized region beneath the extended drain. This localized doped region reduces series resistance only where needed (at the source contact interface) without affecting the overall extended drain structure or requiring additional gate dielectric layers elsewhere in the device.
Solution Approach 2:
The n-type substrate source is formed as a preliminary structure during the extended drain fabrication process, specifically created before final device operation. This preliminary doping action prepares the source region to have low resistance characteristics from the outset, eliminating the need for subsequent resistance reduction steps while maintaining the cost benefits of the extended drain approach.
2Area of stationary object
If charge balanced extended drain is used, then area is reduced, but capacitance remains high in high frequency applications
Solution Approach 1:
The invention applies local quality by introducing an n-type substrate source with specific electrical characteristics in the source region. This localized modification reduces the depletion region capacitance at the source-channel interface, thereby reducing overall device capacitance without increasing the physical transistor area. The n-type doping creates a more favorable potential distribution that minimizes charge storage effects in the compact extended drain structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the performance and reduces power loss in high power and high frequency applications by lowering capacitance and series resistance, while also reducing manufacturing costs through area savings and improved voltage handling.
Implementation Method 1
When a high voltage is placed on the drain, a depletion region forms between the N-substrate and the p-well, between the n-sinker and the p-well, and between the NLDD and the p-well. The drain extension fully depletes so that sufficient high voltage is dropped between the n-sinker and the transistor gate to protect the gate dielectric.
Implementation Method 2
The n-substrate source provides a lower resistance path than power transistors with both a topside source and a topside drain. The n-substrate source and n-sinker provide a lower resistance path than power transistors with both a topside source and a topside drain.
Data Source
AI summary
A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.