Transistor TRIZ Cases

Vertical plugs connect signal lines across stacked NAND cell arrays, reducing substrate space usage and increasing integration density.

Recessing resistors below the gate level preserves protective dielectrics, reducing parasitic capacitance and leakage current.

Selective heat treatment shifts work function values on n-type FinFETs, resolving threshold voltage mismatch with p-type devices.

A segmented trench fabrication method deposits silicon oxide layers to apply tensile stress directly to fin structures.

Bias adjustment circuit modifies driving transistor bias state to stabilize OLED display current.

Homogeneous gate stacks integrate non-volatile memory transistors with standard MOS devices, reducing fabrication complexity and yield loss.

Segmenting nanosheets into narrow and wide regions optimizes gate stack quality while preventing space pinching during dimension reduction.

Parallel aperture arrays expose lower electrode portions to reduce contact area, improving heating efficiency while preventing poor connections.

A trench-type Schottky semiconductor device fabrication method reduces mask layers through oxide spacer formation and plasma planarization.

Backside thermal vias and spreader layers dissipate heat through the buried insulator, resolving SOI thermal isolation trade-offs.

A preventive apparatus adjusts switching thresholds via a constant current circuit to block overcurrents in power systems.

Segments memory into distinct DOSRAM and NOSRAM cells to resolve the trade-off between high-speed access and data stability in semiconductor devices.

A channel-last process uses a lightly doped epitaxial layer to minimize threshold voltage fluctuations in bulk MOS manufacturing.

A protective metal cap shields raised source/drain regions from acid etching damage during dummy gate removal, preserving structural integrity.

Enriched side and bottom surfaces in an indium-containing ternary III-V compound active channel overcome limited carrier mobility in scaled transistors.

An n-type substrate source in a charge balanced extended drain NMOS reduces series resistance and capacitance, lowering manufacturing costs.

An etch stop layer shields the gate profile from acid etchants, resolving stability issues in oxide semiconductor field effect transistors.

Segmented mask processes form a shielding pattern over the active layer to prevent leakage current and improve aperture ratio.

A semiconductor manufacturing method adjusts ion implantation conditions based on measured gate electrode and sidewall insulating film dimensions.

Vertical surrounding gate transistors reduce transistor area by eliminating well isolation and body terminals in compact 3-input NAND circuits.

Composite copper and molybdenum metal film structure enables precise patterning of low-resistance wiring layers in semiconductor manufacturing processes.

A floating gate with a warp-around profile and sharp corner enhances electric field strength.

Dual light shielding films prevent monitor element leakage while maintaining aperture ratio and reducing power consumption.

Step-shaped gate electrodes electrically link vertically stacked nanowires, reducing interconnect congestion in 3D integrated circuits.

Inductive heating of a conductive film crystallizes amorphous silicon while keeping the substrate cool to prevent damage.

A raised layer guides silicide from a deposited metal to the gate electrode while blocking penetration into source/drain junctions.

A threshold voltage control layer with an upwardly protruding junction surface manages channel depletion in semiconductor devices.

A semiconductor bit line uses a barrier metal layer between the contact plug and conductive layer to lower interfacial resistance.

A replacement gate process optimizes high-k dielectric and metal gate layers independently to enable reliable transistor formation.

A fifth doping region disrupts charge flow during discharge events, maintaining high holding voltage and preventing operational voltage drops.

A semiconductor isolation device modulates channel conductance through a high voltage terminal to transfer signals across an insulated barrier.

Vertical fin field effect transistors use germanium concentration gradients to achieve distinct threshold voltages across multiple fins.

A semiconductor device maintains constant discharge current using a field-effect transistor and resistor connected in series.

Retaining photoresist on active layer conductive areas eliminates etch stop layers, reducing array substrate fabrication complexity.

A parasitic vertical PNP bipolar transistor uses shallow trench isolation and shared CMOS implants to form the collector and base regions.

Doped semiconductor layers between graphene sheets enable tunable energy gaps, resolving low on-current and mobility issues from nanoribbon patterning.

A liquid crystal display panel uses a planarizing insulating film to expose source and drain electrodes for direct transparent conductive contact.

Silicon nitride barriers prevent copper diffusion into oxide semiconductors, reducing wiring resistance and display signal delays.

Carbon-based masks facilitate anisotropic etching of gate all around semiconductor devices, resolving access issues in vertically arranged channels.

Forming a buried resistor within the buffer layer of a III-V compound semiconductor device frees channel layer space for high-performance FETs.

Tapered vias link MIM capacitor electrodes to wiring, reducing RF coupling noise.

An adaptive electrostatic discharge protection circuit manages capacitive coupling between drain and gate terminals of MOS devices.

Variable oxide semiconductor layer thicknesses prevent peripheral degradation and reduce threshold voltage dispersion, resolving manufacturing trade-offs.

A depletion transistor incorporates a discharge region to extract minority charge carriers from the channel.

A trench diode uses lateral insulation to reduce charge storage and recovery time.

A semiconductor device design merges active regions to eliminate break region stress.

Controlling the channel supplying layer thickness to 15 nm enables precise electron density regulation for reliable enhancement mode operation.