FinFET CMOS Work Function Modification via Selective Heat Treatment
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Solution Overview
Problem
Current CMOS devices with FinFETs face challenges in achieving optimal work function matching between n-type and p-type fin field effect transistors, affecting threshold voltage control and device performance.
Innovation Solution
A method is developed to form a modified work function material layer on n-type fin FETs through heat treatment, while maintaining unmodified work function materials on p-type fin FETs, allowing for adjacent n-type and p-type FETs with different work functions on the same substrate, enabling effective coupling in CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same work function material is used for both n-type and p-type FinFETs, then the fabrication process is simplified, but the threshold voltage control and device performance deteriorate due to inability to achieve optimal work function matching
Solution Approach 1:
The patent applies local quality by forming a first work function material layer selectively on n-type FinFETs and a second work function material layer selectively on p-type FinFETs. This allows different work function materials to be used for different device types, optimizing threshold voltage control for each while maintaining a unified fabrication process flow through selective deposition and heat treatment steps.
2Manufacturing precision
If different work function materials are used for n-type and p-type FinFETs, then threshold voltage control is improved, but the fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct selective steps: forming a first work function material layer on n-type FinFETs, performing heat treatment to modify its work function, then forming a second work function material layer on p-type FinFETs. This segmentation allows different materials to be applied to different device types through a systematic multi-step process, achieving precise threshold voltage control without overwhelming complexity.
Solution Approach 2:
The patent applies preliminary action by first forming and heat-treating the work function material layer on n-type FinFETs before forming the work function material layer on p-type FinFETs. This sequential approach allows the n-type device characteristics to be established first, then the p-type devices to be processed, simplifying the overall process management while achieving different work function optimization for each device type.
3Measurement precision
If heat treatment is applied to modify work function, then threshold voltage adjustment precision is improved, but the process temperature and energy consumption increase
Solution Approach 1:
The patent utilizes parameter changes by applying heat treatment to modify the work function of the first work function material layer on n-type FinFETs. This thermal processing changes the electrical properties of the material, enabling precise threshold voltage adjustment. The heat treatment is applied selectively only to regions with the first work function material, optimizing energy usage while achieving the desired electrical characteristic modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise threshold voltage adjustment of n-type transistors and maintains optimal performance of p-type transistors, enhancing the overall functionality and efficiency of CMOS devices by ensuring accurate electrical joining of gate structures.
Implementation Method 1
heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value
Data Source
AI summary
A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.