Oxide Semiconductor FET Gate Protection and Etch Stop

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Solution Overview

Problem

Oxide semiconductor field effect transistors (OS FETs) are sensitive to environmental changes such as water, oxygen, and acid etchants, making their channel layer unstable during manufacturing, which affects their characteristics.

Innovation Solution

The OS FET device includes a gate electrode that covers the channel region and an etch stop layer to protect it, along with a self-align source/drain process that prevents damage to the gate electrode profile, ensuring stability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the OS channel layer is exposed during manufacturing processes, then the manufacturing process can be completed, but the OS channel layer becomes sensitive to environmental impacts such as water, oxygen, and acid etchants, affecting device stability

Engineering Contradiction:
Improvemanufacturing process accessibilityVSAvoidOS channel layer stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate electrode is formed to cover and protect the OS channel layer before subsequent manufacturing steps are performed. This preliminary protective action prevents environmental contaminants from damaging the sensitive OS channel layer during later processing steps, resolving the contradiction by enabling manufacturing access while maintaining channel layer stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate electrode serves as an intermediary protective layer between the OS channel layer and the harsh manufacturing environment. It acts as a barrier that allows manufacturing processes to proceed while preventing direct exposure of the OS channel layer to harmful substances like water, oxygen, and acid etchants.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If conventional manufacturing processes are used without protective structures, then the process flow is simpler, but the gate electrode profile may be damaged during self-align source/drain processes

Engineering Contradiction:
Improveprocess structureVSAvoidgate electrode profile integrity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The etch stop layer is deposited beforehand to cushion and protect the gate electrode profile during subsequent self-align source/drain etching processes. This protective layer prevents the etchant from directly attacking the gate electrode, thereby maintaining manufacturing precision while using a relatively simple process structure.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If the OS FET device is manufactured with exposed channel region, then manufacturing steps can be performed, but the device characteristics change due to environmental exposure

Engineering Contradiction:
Improvemanufacturing throughputVSAvoiddevice characteristic stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate electrode is formed to cover the OS channel layer before subsequent manufacturing steps, preventing environmental exposure that would alter device characteristics. This allows manufacturing to proceed with normal throughput while maintaining stable device characteristics throughout the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9455351B1Oxide semiconductor field effect transistor device and method for manufacturing the same
Publication Date: 2016.09.27 UNITED MICROELECTRONICS CORP
  • US9455351B1 patent drawing
  • US9455351B1 patent drawing
  • US9455351B1 patent drawing

AI summary

An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.