Oxide Semiconductor Thickness Variation in TFT Array Panels
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Solution Overview
Problem
Current thin film transistor array panels face limitations in manufacturing high-performance transistors due to low charge mobility in amorphous silicon and high cost, low uniformity, and size constraints with polysilicon, necessitating the development of oxide semiconductor layers with variable thickness for improved performance and cost-effectiveness.
Innovation Solution
A thin film transistor array panel design featuring oxide semiconductor layers with varying thicknesses in display and peripheral areas, where the first semiconductor layer in the display area and the second semiconductor layer in the peripheral area are formed with indium, gallium, and zinc, with the second semiconductor layer being thicker to reduce threshold voltage dispersion and prevent degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used for the semiconductor layer, then the manufacturing cost is low and the process is simple, but the charge mobility is low which limits high-performance transistor manufacturing
Solution Approach 1:
The patent changes the material composition parameters of the semiconductor layer by incorporating multiple metal elements (In, Ga, Zn) in specific ratios within the oxide semiconductor structure. This compositional parameter optimization enables simultaneous achievement of high charge mobility and manufacturing feasibility, resolving the contradiction between manufacturing simplicity and charge mobility.
2Reliability
If polysilicon is used for the semiconductor layer, then the charge mobility is high enabling high-performance transistors, but the manufacturing cost increases and uniformity decreases for large-sized panels
Solution Approach 1:
The patent modifies the semiconductor material parameters by using oxide semiconductor with specific metal element compositions (In-Ga-Zn-O system) instead of conventional polysilicon. This material parameter change achieves high charge mobility comparable to polysilicon while maintaining the manufacturing advantages of low cost and high uniformity across large panels.
Solution Approach 2:
The patent employs a composite oxide semiconductor structure containing multiple metal elements (Indium, Gallium, Zinc) combined with oxygen. This composite material approach synergistically combines the high charge mobility characteristics needed for performance with the manufacturing advantages of oxide semiconductors, overcoming the limitations of both amorphous silicon and polysilicon.
3Ease of manufacture
If a uniform thickness oxide semiconductor layer is used across the entire panel, then the manufacturing process is simple, but threshold voltage dispersion occurs in the display area and degradation occurs in the peripheral area
Solution Approach 1:
The patent applies different thickness specifications for oxide semiconductor layers in different panel regions: a first thickness for the display area and a second thickness for the peripheral area. This local differentiation optimizes transistor performance in each region, preventing threshold voltage dispersion in the display area and degradation in the peripheral area, while maintaining overall process feasibility.
4Reliability
If the oxide semiconductor layer thickness is increased to prevent degradation in peripheral area, then the reliability improves, but threshold voltage dispersion increases in the display area
Solution Approach 1:
The patent implements region-specific thickness control where the oxide semiconductor layer has a first thickness in the display area optimized for threshold voltage uniformity, and a second thickness in the peripheral area optimized for degradation prevention. This localized quality approach allows each region to have the optimal thickness for its specific functional requirements, resolving the contradiction between degradation prevention and threshold voltage uniformity.
Data Source
AI summary
Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.