Vertical FinFETs with Germanium Grading for Multiple Threshold Voltages
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Solution Overview
Problem
As device dimensions decrease, forming individual components and electrical contacts in traditional Field Effect Transistors (FETs) becomes increasingly difficult due to scaling issues, particularly with channel lengths and gate dielectric thicknesses, necessitating a method to retain positive aspects while overcoming these challenges.
Innovation Solution
The method involves forming vertical fin field effect transistors (FinFETs) with varying germanium concentrations by creating a silicon-germanium cap layer on a substrate, forming multiple vertical fins, and using different germanium doping layers to achieve distinct threshold voltages through germanium diffusion and removal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are decreased to improve integration density, then productivity increases, but manufacturing precision deteriorates due to difficulty in forming individual components and electrical contacts
Solution Approach 1:
The patent transitions from planar FET structures to vertical FinFET structures, moving the channel formation from the substrate plane to the vertical dimension. This dimensional change allows continued scaling in the lateral plane while maintaining manufacturable channel lengths and gate dielectric thicknesses through vertical channel extension, thereby improving integration density without sacrificing manufacturing precision
Solution Approach 2:
The patent applies different germanium concentrations at different locations within the vertical fin structure to achieve multiple threshold voltages. By creating regions with varying germanium content (higher Ge concentration for lower threshold voltage, lower Ge concentration for higher threshold voltage), the invention enables localized optimization of transistor characteristics while maintaining the overall vertical structure, thus improving manufacturing precision for multi-threshold devices
2Productivity
If device dimensions are decreased to improve integration density, then productivity increases, but reliability deteriorates due to scaling issues with channel lengths and gate dielectric thicknesses
Solution Approach 1:
By transitioning to vertical FinFET structures, the patent extends the channel into the vertical dimension, allowing the effective channel length to be maintained at reliable dimensions even as lateral dimensions are scaled down. This dimensional transition preserves device reliability while enabling higher integration density through reduced lateral footprint
Solution Approach 2:
The patent modifies the germanium concentration parameter within the fin structure to control threshold voltage and improve device reliability. By adjusting germanium content in specific regions, the invention optimizes carrier mobility and threshold voltage characteristics, thereby maintaining reliable device performance at scaled dimensions while improving integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of FinFETs with multiple threshold voltages, enabling improved control over transistor performance and addressing scaling issues in smaller device components, enhancing the reliability and efficiency of logic devices.
Implementation Method 1
forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps
Data Source
AI summary
A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.