Integrated DOSRAM and NOSRAM Memory Fabrication
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Solution Overview
Problem
Current semiconductor memory devices struggle to integrate high-density dynamic random access memory (DRAM) and low-leakage non-volatile memory (NVM) on a single chip, as DRAM is volatile and power-consuming, while NVM is slower and requires higher programming voltages, affecting endurance.
Innovation Solution
A semiconductor memory device is developed with integrated dynamic oxide semiconductor random access memory (DOSRAM) and non-volatile oxide semiconductor random access memory (NOSRAM) cells, utilizing oxide semiconductor field effect transistors (OS FETs) and metal-insulator-metal (MIM) capacitors on a single chip, enabling both high-density DRAM and low-leakage NVM integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for high-density memory integration, then fast access speed is achieved, but data stability and non-volatility deteriorate
Solution Approach 1:
The patent segments the memory device into two distinct types: DOSRAM cells for volatile high-speed storage and NOSRAM cells for non-volatile stable storage. Each cell type is independently designed with appropriate transistor and capacitor configurations, allowing the system to leverage both fast access and data stability without compromise
Solution Approach 2:
The patent creates a universal memory architecture where both DOSRAM and NOSRAM cells share common structural elements (oxide semiconductor transistors, capacitor designs, interconnect schemes) while serving different functional purposes. This multi-functional approach enables a single chip to provide both volatile and non-volatile memory capabilities
2Reliability
If NVM is used for non-volatile storage, then data stability is improved, but access speed deteriorates
Solution Approach 1:
The patent segments the memory device into two distinct types: DOSRAM cells for volatile high-speed storage and NOSRAM cells for non-volatile stable storage. Each cell type is independently designed with appropriate transistor and capacitor configurations, allowing the system to leverage both fast access and data stability without compromise
Solution Approach 2:
The patent creates a universal memory architecture where both DOSRAM and NOSRAM cells share common structural elements (oxide semiconductor transistors, capacitor designs, interconnect schemes) while serving different functional purposes. This multi-functional approach enables a single chip to provide both volatile and non-volatile memory capabilities
3Quantity of substance
If DRAM and NVM are integrated on one chip, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by assigning different transistor and capacitor configurations to specific regions of the chip. DOSRAM cells use one configuration optimized for speed, while NOSRAM cells use another configuration optimized for non-volatility, allowing each local region to have the properties best suited for its intended function
Solution Approach 2:
The patent creates a universal memory architecture where both DOSRAM and NOSRAM cells share common structural elements (oxide semiconductor transistors, capacitor designs, interconnect schemes) while serving different functional purposes. This multi-functional approach enables a single chip to provide both volatile and non-volatile memory capabilities
Data Source
AI summary
A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.