Ion Implantation Feedback for eDRAM On-Current Uniformity
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Solution Overview
Problem
The manufacturing process of eDRAM devices results in significant variations in on-current among semiconductor wafers due to inconsistencies in gate length and sidewall insulating film dimensions, affecting the writing and reading characteristics of DRAM cells.
Innovation Solution
A method involving the measurement and feedback of design dimensions for gate electrodes and sidewall insulating films, followed by resetting ion implantation conditions to form high-concentration semiconductor regions, ensuring precise formation of these regions to reduce variations in electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation conditions are set according to design dimensions without measurement feedback, then manufacturing process is simple, but variations in gate length and sidewall insulating film dimensions cause significant variations in on-current among semiconductor wafers
Solution Approach 1:
The patent implements a feedback mechanism where the actual dimensions of gate electrodes and sidewall insulating films are measured, and these measurement results are used to reset and adjust ion implantation conditions. This closed-loop control ensures that variations in dimensional parameters are compensated by adjusting ion implantation dosage, thereby reducing on-current variations across wafers while maintaining a manageable manufacturing process
Solution Approach 2:
The patent dynamically adjusts ion implantation parameters (dosage, energy) based on measured dimensional variations of gate electrodes and sidewall insulating films. By changing the ion implantation conditions according to actual measurements, the method compensates for dimensional deviations and achieves uniform electrical characteristics across different wafers
2Reliability
If design dimensions are strictly controlled without considering actual processed dimensions, then manufacturing process is straightforward, but electrical characteristics of DRAM cells vary significantly affecting writing and reading performance
Solution Approach 1:
The patent performs preliminary measurements of gate electrode and sidewall insulating film dimensions before ion implantation. These advance measurements allow the manufacturing process to be adjusted based on actual dimensions, ensuring that ion implantation conditions are optimized for each specific wafer condition, thereby improving DRAM cell performance consistency
Solution Approach 2:
The patent uses measurement feedback to adjust ion implantation conditions. The actual dimensions of gate electrodes and sidewall insulating films are measured, and these results feed back into the ion implantation process to reset dosage and energy parameters, ensuring that electrical characteristics remain consistent across wafers despite dimensional variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical characteristics of DRAM cells by reducing variations in threshold voltage and on-current, enhancing the writing and reading performance of DRAM cells.
Implementation Method 1
a first ion implantation step for forming a low-concentration semiconductor region at each end of the gate electrode; a second ion implantation step for forming a high-concentration semiconductor region
Data Source
AI summary
A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed.