Channel-Last MOSFET Doping for Threshold Voltage Variability
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Solution Overview
Problem
The variability in threshold voltage of metal-oxide semiconductor field effect transistors (MOSFETs) due to random dopant fluctuations, line edge roughness, and random extension fluctuations undermines the reproducibility of threshold voltages among identical transistors, particularly in bulk MOS manufacturing, which is exacerbated as MOSFETs shrink in size.
Innovation Solution
A 'channel-last' process is introduced, where a lightly doped epitaxial layer is formed within a cavity beneath the gate, reducing dopant diffusion and variations in channel length, and a highly doped buried layer is used to minimize threshold voltage fluctuations, while maintaining the cost advantages of standard bulk MOS manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are shrunk to finer dimensions to increase integration density, then productivity and device miniaturization are improved, but threshold voltage variability due to random dopant fluctuations increases
Solution Approach 1:
The channel region is segmented into two distinct doping zones: a lightly-doped epitaxial layer at the interface with the gate dielectric and a heavily-doped buried layer deeper in the substrate. This segmentation allows the first region to minimize interface effects and the second region to control bulk doping, thereby reducing random dopant fluctuations while maintaining high integration density
Solution Approach 2:
Different regions of the channel are given different doping qualities - the interface region is lightly-doped to reduce variability, while the bulk region is heavily-doped to maintain carrier concentration. This local differentiation of doping quality reduces threshold voltage variability without sacrificing device performance or integration density
2Ease of manufacture
If traditional bulk MOS manufacturing is used to maintain cost-effectiveness, then ease of manufacture is improved, but threshold voltage reproducibility deteriorates
Solution Approach 1:
The lightly-doped epitaxial layer is formed preliminarily before final device fabrication steps. This preliminary action establishes a controlled doping profile at the critical interface region, preventing random dopant fluctuations from affecting threshold voltage reproducibility while maintaining compatibility with standard bulk MOS manufacturing processes
Solution Approach 2:
The device structure uses a composite doping approach combining lightly-doped and heavily-doped regions within the channel. This composite structure leverages the advantages of both doping levels - reduced variability from the lightly-doped interface region and sufficient carrier concentration from the heavily-doped bulk region - achieving improved reproducibility within cost-effective bulk manufacturing
3Quantity of substance
If heavily doped regions are used to maintain carrier concentration, then electrical conductivity is improved, but random dopant fluctuations increase causing threshold voltage variability
Solution Approach 1:
The doping structure is segmented into a lightly-doped epitaxial layer near the gate interface and a heavily-doped buried layer deeper in the substrate. The lightly-doped region contains fewer dopant atoms to minimize random fluctuations, while the heavily-doped buried layer provides sufficient carrier concentration through thermal diffusion, thus resolving the contradiction between conductivity and variability
Solution Approach 2:
The lightly-doped epitaxial layer acts as an intermediary between the gate dielectric and the heavily-doped bulk substrate. This intermediary layer reduces the direct impact of high dopant concentrations on the critical interface, minimizing random dopant fluctuations while still allowing the heavily-doped buried layer to contribute carriers through diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces variations in threshold voltage, improving the reproducibility of MOSFETs and allowing for adjustment of threshold voltage values, while maintaining the simplicity and cost-effectiveness of bulk MOS manufacturing processes.
Implementation Method 1
reduces the diffusion of dopants from the heavily doped region beneath the low-doped epitaxial layer into the low-doped epitaxial layer
Implementation Method 2
an ion implant step through the cavity results in localized increase in well-doping directly beneath the cavity
Implementation Method 3
The implant is activated by a microsecond annealing which causes minimum dopant diffusion
Implementation Method 4
a high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed
Data Source
AI summary
Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.