Threshold Voltage Control Layer in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving complete depletion of the channel region below the drain-side end portion of the gate electrode, leading to reduced current gain due to difficulties in implanting impurities in shallow areas, which complicates the formation of a shallow LDD region.
Innovation Solution
A semiconductor device structure featuring a threshold voltage control layer with an upwardly protruding junction surface between the extension region and the channel region, eliminating the need for pocket implantation regions by forming an extension region with a second conductivity type and a threshold voltage control layer with a concentration peak at a shallower position, allowing complete depletion and enhanced current gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pocket implantation region is provided under the LDD structure to improve current gain, then the output impedance increases and current gain improves, but the device complexity increases and manufacturing precision requirements increase
Solution Approach 1:
The invention extracts and eliminates the pocket implantation region from the device structure, replacing it with a threshold voltage control layer that has an upwardly protruding junction surface. This removes the need for the additional implantation step and associated complexity while maintaining the current gain improvement through complete depletion of the channel region below the gate electrode.
Solution Approach 2:
The threshold voltage control layer is designed with a specific local property: an upwardly protruding junction surface with the extension region. This localized structural feature creates complete depletion in the critical area below the gate electrode, achieving the current gain improvement without requiring the broader pocket implantation region structure.
2Reliability
If the LDD region is made shallow to achieve complete depletion of the channel region, then current gain improves, but manufacturing precision becomes more difficult due to inability to implant impurity in shallow portions below gate electrode end
Solution Approach 1:
Instead of trying to implant impurities into the shallow channel region below the gate electrode end (which is manufacturing-difficult), the invention inverts the approach by creating a threshold voltage control layer with an upwardly protruding junction surface. This structural inversion achieves complete depletion through the geometry of the junction surface itself rather than through direct shallow implantation.
Solution Approach 2:
The threshold voltage control layer is formed with a predetermined impurity concentration profile and upwardly protruding junction surface configuration before final device operation. This preliminary structuring ensures that complete depletion occurs automatically when the device is operated, without requiring precise control of shallow implantation processes.
3Reliability
If the threshold voltage control layer has an upwardly protruding junction surface with the extension region, then complete depletion is achieved and current gain improves, but the manufacturing process complexity increases
Solution Approach 1:
The invention merges the threshold voltage control function with the channel depletion function into a single integrated structure. The threshold voltage control layer serves dual purposes: controlling the threshold voltage through its impurity concentration and achieving complete depletion through its upwardly protruding junction surface geometry, thereby reducing the need for separate structural elements.
Solution Approach 2:
The threshold voltage control layer is designed to perform multiple functions simultaneously: it controls the threshold voltage of the device, creates complete depletion in the channel region below the gate electrode, and eliminates the need for separate pocket implantation regions. This multi-functionality reduces overall device complexity despite the specialized structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures complete depletion of the channel region below the gate electrode, suppressing channel length variations and increasing the absolute value of early voltage, thereby improving current gain and analog characteristics in MIS transistors.
Implementation Method 1
a threshold voltage control layer for controlling a threshold voltage, the threshold voltage control layer being formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region
Implementation Method 2
an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in a gate-length direction of the gate electrode and the threshold voltage control layer
Data Source
AI summary
A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto. The junction surface between the threshold voltage control layer and the extension region has an upwardly protruding configuration.