3D Nanowire Transistors With Step-Shaped Gate Electrodes
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors to smaller sizes, particularly in achieving three-dimensional (3D) integration of circuits where transistors are stacked vertically, due to complexities in interconnects and area scaling limitations in two-dimensional (2D) circuits.
Innovation Solution
The development of a 3D integrated circuit with vertically stacked nanowires and a step-shaped connecting structure within the gate region, allowing for individual electrical connections to each nanowire, which enables self-aligned contact formation and reduces congestion in metallization layers, facilitating area scaling by stacking n-type and p-type transistors on top of each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional (2D) circuit scaling is continued, then transistor density increases, but area scaling limitations and manufacturing complexity worsen
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked nanowire transistors. Multiple nanowires are stacked vertically within a single footprint, enabling continued transistor density improvement while maintaining manageable manufacturing complexity through standardized vertical stacking processes.
Solution Approach 2:
The transistor channel is segmented into multiple discrete nanowires stacked vertically. Each nanowire acts as an independent channel, allowing parallel processing and simplified manufacturing compared to scaling a single large planar transistor, thereby improving density without proportionally increasing complexity.
2Area of stationary object
If three-dimensional (3D) transistor stacking is implemented, then area scaling improves, but interconnect complexity and manufacturing difficulty worsen
Solution Approach 1:
Multiple nanowire transistors are merged into a single vertical stack sharing common source and drain regions. This merging reduces the number of discrete interconnects needed compared to separate planar transistors, improving area scaling while controlling interconnect complexity through shared structures.
Solution Approach 2:
The vertical stack structure serves multiple functions simultaneously: it provides electrical isolation between nanowires, mechanical support, and a framework for common source/drain connections. This multi-functionality reduces the number of separate components needed, simplifying interconnect architecture.
3Quantity of substance
If vertically stacked nanowires are formed, then transistor density increases, but fabrication process complexity worsens
Solution Approach 1:
Nanowires are pre-formed on substrates and then transferred to the final device location. This preliminary formation allows standardized, simplified nanowire fabrication processes to be used separately from the complex integration steps, reducing overall fabrication complexity while maintaining high transistor density.
Solution Approach 2:
A transfer mechanism serves as an intermediary between nanowire fabrication and device assembly. The nanowires are fabricated on a separate substrate, transferred, and then integrated into the vertical stack, decoupling the fabrication complexity from the final device structure and enabling modular manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for significant area scaling benefits by enabling individual connections to each terminal in the circuit, simplifying the layout of metallization layers, and reducing the footprint of 3D SRAM cells, while maintaining efficient electrical access and isolation between nanowires.
Implementation Method 1
The horizontal barrier being formed by selectively depositing barrier material on the temporary surface without depositing barrier material on the second-level nanowire
Data Source
AI summary
A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.