Raised Layer Silicidation for CMOS Gate and Source/Drain
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Solution Overview
Problem
Conventional silicidation processes for CMOS devices face issues such as potential work function drift, silicide penetration into the channel region, and increased complexity and cost due to multiple process steps, particularly when siliciding gates before source/drain activation.
Innovation Solution
A method involving the formation of a raised layer adjacent the gate and source/drain, followed by depositing a silicidation layer and siliciding the raised layer to substantially silicide the gate, which avoids junction penetration and simplifies the process by reducing the number of masking and removal steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate is silicided before the source/drain activation, then the gate can be fully silicided, but the high activation temperatures can drive the silicide through the gate dielectric and into the channel region, causing potential work function drift
Solution Approach 1:
The source/drain regions are activated (doped) before the gate silicidation process. This preliminary action ensures that the source/drain junctions are already formed and stabilized, so that subsequent high-temperature silicidation of the gate does not cause silicide penetration into the channel region. The sequence is reversed from conventional processes: source/drain activation occurs first, then gate silicidation follows.
2Reliability
If two different silicidation steps are performed with different metal thicknesses for gate and source/drain, then the problems of work function drift and silicide penetration are addressed, but the process complexity and cost increase due to separate masking and removal steps
Solution Approach 1:
The gate and source/drain silicidation processes are merged into a single simultaneous treatment step. A uniform silicidation layer is deposited over both regions, and both are silicided together in one thermal processing step. This eliminates the need for separate masking, deposition, and removal steps for each region, significantly simplifying the process while maintaining the reliability benefits of proper silicidation control.
Solution Approach 2:
A single silicidation layer serves multiple functions: it silicides both the gate electrode and the source/drain regions simultaneously. The same deposition and thermal processing conditions are used for both structures, making the process universal and eliminating the need for region-specific process parameters or additional process steps.
3Manufacturing precision
If the source/drain are silicided before the gate electrodes, then the source/drain can be silicided, but the silicide penetrates deeper into the source/drain junction due to thickness differences, rendering the device inoperable or causing shorts
Solution Approach 1:
The source/drain regions are activated (doped) before the simultaneous silicidation process. This preliminary doping action ensures that the source/drain junctions are already formed with appropriate electrical characteristics. When silicidation occurs subsequently, the silicide formation is controlled and does not penetrate excessively into the already-formed junctions, preventing shorts and device failure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents silicide penetration into the source/drain junction, reduces manufacturing complexity and cost, and ensures reliable device operation by allowing full silicidation of the gate without compromising the source/drain junction, thereby improving the efficiency and effectiveness of the silicidation process.
Implementation Method 1
depositing a silicidation layer over the gate and the raised layer, and siliciding the raised layer and substantially siliciding the gate with the silicidation layer
Data Source
AI summary
In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].