Semiconductor Bit Line Barrier Metal Layer Design
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Solution Overview
Problem
Conventional semiconductor device manufacturing methods face challenges in reducing unit cell size to increase memory device density, as short bit line conductive layers lead to high resistance, while tall layers result in parasitic capacitance and structural instability, complicating the formation of bit lines and gate electrodes.
Innovation Solution
A barrier metal layer is formed between the bit line contact plug and conductive layer, reducing interfacial resistance, increasing the thickness of the bit line conductive layer, and lowering the overall bit line height to minimize parasitic capacitance, achieved through a laminated structure with a polysilicon contact plug and tungsten conductive layers, and a nitride spacer material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bit line conductive layer is formed to be short (shallow), then the manufacturing process is simpler, but resistance of the bit line conductive layer deteriorates
Solution Approach 1:
The patent uses a composite structure consisting of a contact plug, barrier metal layer, and bit line conductive layer. The barrier metal layer (e.g., titanium nitride or tungsten silicide) is positioned between the contact plug and conductive layer to reduce interfacial resistance, while the conductive layer (e.g., tungsten or copper) provides low resistance conduction. This composite material approach allows the bit line conductive layer to be formed shallowly without compromising resistance performance.
Solution Approach 2:
The patent applies different material properties to different regions: the barrier metal layer is specifically placed at the interface region between the contact plug and conductive layer where interfacial resistance is highest, while the main conductive layer provides bulk conduction. This localized application of specialized materials optimizes resistance without requiring increased overall height.
2Reliability
If the bit line conductive layer is formed to be tall (thick), then resistance is reduced, but parasitic capacitance between the bit line conductive layer and storage node contact becomes severe
Solution Approach 1:
The barrier metal layer acts as an intermediary between the contact plug and the bit line conductive layer. By positioning this layer at the interface, it reduces interfacial resistance without requiring the conductive layer to be taller, thereby avoiding increased parasitic capacitance between the bit line and storage node contact.
3Reliability
If the bit line conductive layer is formed to be tall (thick), then resistance is reduced, but the bit line conductive layer is prone to collapse
Solution Approach 1:
The patent employs a composite structure with a barrier metal layer and conductive layer. The barrier metal layer provides structural support at the critical interface region, enabling the conductive layer to be formed with sufficient thickness for low resistance without compromising structural stability and avoiding collapse.
4Productivity
If a bit line of the cell region and gate electrode of the peripheral circuit are simultaneously formed, then productivity is improved, but a shadowing effect occurs in tilt implantation process
Solution Approach 1:
The patent forms different structures in different regions: in the cell region, a shallow bit line conductive layer is formed simultaneously with the gate electrode, while in the peripheral region, the gate electrode is formed separately. The barrier metal layer is selectively positioned to enable this differential formation, reducing shadowing effects during tilt implantation while maintaining productivity through simultaneous formation in the cell region.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.