Stacked NAND Memory Device Vertical Signal Routing
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Solution Overview
Problem
Conventional non-volatile memory devices with a stacked structure face challenges in integrating a complex arrangement of cell arrays and peripheral circuits, limiting their integration density due to complicated signal line connections.
Innovation Solution
A non-volatile memory device with a stacked structure that includes a substrate, vertically stacked NAND cell arrays, and signal lines arranged either under or on the substrate, simplifying connections through vertical plugs, allowing for reduced substrate space usage and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked structure is used to increase integration density, then memory capacity is improved, but signal line connection complexity increases
Solution Approach 1:
The patent transitions from planar 2D connections to 3D vertical connections by stacking multiple NAND cell arrays vertically. Signal lines extend vertically through the stacked structure, enabling connections between different memory layers without requiring complex lateral routing, thus increasing integration density while managing connection complexity through vertical dimension utilization.
Solution Approach 2:
The patent implements a hierarchical nested structure where multiple NAND cell arrays are stacked vertically, with each array containing multiple strings. Signal lines are nested within the stacked structure, routing through intermediate layers to connect memory cells across different stacks, creating a compact nested architecture that improves capacity while organizing connections systematically.
2Area of stationary object
If vertically stacked NAND strings are implemented to reduce substrate space, then integration density is improved, but arrangement complexity of cell array and peripheral circuit increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple NAND cell arrays vertically on the substrate, thereby reducing the lateral footprint and increasing integration density. This vertical stacking allows more memory capacity to be packed into the same substrate area by exploiting the third dimension rather than expanding horizontally.
Solution Approach 2:
The patent divides the memory structure into multiple segmented NAND cell arrays stacked vertically, with each array containing multiple strings. This segmentation allows independent optimization of each stack and facilitates modular manufacturing, reducing overall arrangement complexity by breaking down the complex 3D structure into manageable repeating units.
Data Source
AI summary
Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.