Replacement Metal Gate CMOS Process for Interdiffusion Control
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Solution Overview
Problem
Conventional high-k metal gate CMOS manufacturing processes face challenges with interdiffusion between differing work function metal gate layers and difficulties in filling narrow gaps within p-channel transistor gate structures, leading to non-uniform transistor performance and reliability issues.
Innovation Solution
A replacement gate process is implemented where the thickness and composition of high-k gate dielectric materials for n-channel and p-channel MOS transistors are independently controlled, avoiding interdiffusion by using separate dummy gate structures and optimizing the interface layers, allowing for better step coverage and fill characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metal gate layers are used for n-channel and p-channel transistors to achieve different work functions, then transistor performance is improved, but interdiffusion between metal layers occurs causing reliability issues
Solution Approach 1:
The gate structure is segmented into separate n-channel gate and p-channel gate regions with distinct metal layers deposited independently. This segmentation allows different work function metals to be used for each transistor type without interdiffusion, as each metal layer is confined to its designated region by the dummy gate structure removal process.
Solution Approach 2:
A dummy gate structure (polysilicon gate) is used as an intermediary placeholder during the deposition of different metal gate layers. The dummy gate is selectively removed after metal deposition, allowing the different metal layers to be deposited without direct contact or interdiffusion, while still enabling subsequent gate formation.
2Ease of manufacture
If conventional high-k metal gate CMOS manufacturing processes are used, then manufacturing simplicity is maintained, but narrow gap filling difficulties occur in p-channel transistor gate structures
Solution Approach 1:
The dummy gate structure is removed after metal gate layer deposition but before final gate formation. This preliminary removal creates adequate gap space that allows subsequent metal fill material to be deposited uniformly without the narrow gap filling problems that would occur if the gate structure remained in place during metal deposition.
3Reliability
If high-k gate dielectric materials are used to prevent gate current leakage, then dielectric integrity is improved, but interface layer quality degradation occurs
Solution Approach 1:
The gate dielectric structure uses a composite of high-k dielectric material (for high dielectric constant and thin film capability) combined with a carefully engineered interface layer (for quality and low defect density). This composite structure allows the high-k material to prevent gate leakage while the interface layer maintains electrical integrity and reduces interface states.
Data Source
AI summary
A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.