Nanosheet Gate Stack Optimization for Electrostatic Control
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Solution Overview
Problem
Current nanosheet devices face challenges in achieving improved gate properties and electrostatic control, particularly in maintaining sidewall and top nanosheet gate dielectric quality, which affects device performance and dimension reduction.
Innovation Solution
The method involves forming a gate-all-around structure on nanosheet devices with narrow and wide nanosheets on a substrate, using an interfacial layer, gate dielectric layer, and a conductive gate layer, along with a dummy gate and cover layer, and annealing a blocking layer to enhance gate stack quality and electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around structure is formed on nanosheet devices with narrow and wide nanosheets, then electrostatic control and gate stack quality are improved, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
The nanosheet device is segmented into narrow and wide nanosheet regions, each optimized for specific functions. The gate structure is segmented into different layers (interfacial layer, gate dielectric layer, conductive gate layer) deposited at different stages, allowing independent optimization of each segment's properties while achieving overall improved electrostatic control
Solution Approach 2:
The gate-all-around structure implements a nested configuration where the interfacial layer is nested within the gate dielectric layer, which is in turn nested around the conductive gate layer that completely surrounds the nanosheet channel. This nested arrangement maximizes gate control over the channel while maintaining a structured, manufacturable process sequence
2Productivity
If the nanosheet device dimensions are reduced to improve performance, then device performance is enhanced, but the gate dielectric quality and electrostatic control deteriorate
Solution Approach 1:
Different regions of the nanosheet device are assigned different qualities and dimensions. Narrow nanosheets and wide nanosheets have different width dimensions optimized for their respective roles. The gate stack layers are deposited with locally optimized thicknesses and materials to maintain high gate dielectric quality even as overall device dimensions are reduced
Solution Approach 2:
The interfacial layer is formed preliminarily before the gate dielectric layer deposition. This preliminary formation of a high-quality interfacial layer provides a stable foundation that maintains gate dielectric quality even when subsequent dimension reductions are applied to the overall device structure
3Productivity
If spaces between nanosheets are reduced to improve device integration, then device integration is improved, but pinching off of spaces occurs which degrades device performance
Solution Approach 1:
The distance between adjacent nanosheets is precisely controlled within the range of 5.5 nm to 17.5 nm. This parameter optimization allows sufficient spacing to prevent pinching off during fabrication and operation, while minimizing the space to achieve high device integration density. The conductive gate layer configuration further modifies the electric field distribution to prevent pinching effects at these reduced dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electrostatic control and gate stack quality, preventing pinching off of spaces between nanosheets, and is applicable to digital logic and memory devices, enabling further device dimension reduction and performance enhancement.
Implementation Method 1
forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets, wherein the interfacial layer is a semiconductor oxide
Implementation Method 2
annealing a blocking layer to enhance gate stack quality and electrostatic control
Data Source
AI summary
A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.