Floating Gate Warp-Around Profile for Erasing Efficiency
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Solution Overview
Problem
Non-volatile memory devices face challenges in controlling the erasing efficiency due to the difficulty in fabricating a consistent side profile of the floating gate, leading to over-erasing phenomena and reading errors.
Innovation Solution
A non-volatile memory device with a floating gate having a warp-around profile and a sharp corner is fabricated using a controllable process, enhancing the electric field strength and erasing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional floating gate with vertical sidewalls is used, then the fabrication process is simple, but the erasing efficiency is insufficient and over-erasing occurs
Solution Approach 1:
The floating gate sidewalls are transformed from vertical straight lines to curved warp-around profiles that extend laterally over the source and drain regions. This curvature increases the electric field strength at the corners and along the sidewalls, thereby improving electron tunneling efficiency during erasing operations without requiring complex additional fabrication steps
Solution Approach 2:
The sidewall angle parameter is changed from vertical (90 degrees) to a curved profile with varying angles. The warp-around profile creates regions with smaller effective angles at the corners, which concentrates the electric field and enhances tunneling current, improving erasing efficiency while maintaining fabrication simplicity
2Reliability
If the sidewall profile is made complex to improve erasing efficiency, then the electric field strength increases, but the manufacturing precision and profile consistency become difficult to control
Solution Approach 1:
The curved warp-around profile is achieved through a controlled fabrication process that creates consistent lateral extension of the floating gate material. The curvature radius and extension distance are precisely controlled during deposition, ensuring uniform profiles across all floating gates while maintaining the enhanced electric field characteristics
Solution Approach 2:
The floating gate material is deposited to extend laterally over the source and drain regions before the source and drain are fully formed. This preliminary extension creates the warp-around profile in advance, ensuring consistent geometry is established early in the fabrication process when dimensional control is most effective
3Productivity
If excessive electrons are ejected from the floating gate during erasing, then the erasing process is aggressive, but the channel turns on prematurely causing reading errors
Solution Approach 1:
The warp-around profile creates localized regions of high electric field strength at the corners and along the curved sidewalls, while the top and bottom regions maintain moderate field strength. This spatial variation in field quality enables controlled electron emission that prevents excessive ejection and subsequent channel turn-on, improving reading accuracy while maintaining efficient erasing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The warp-around profile and sharp corner of the floating gate improve erasing efficiency, reliability, and read-out current strength, preventing over-erasing and reducing data read-out errors.
Implementation Method 1
Based on Flower-Nordheim (FN) tunneling, which is a common way to erase data, carriers can flow between the floating gate and the erasing gate.
Implementation Method 2
a floating gate having a warp-around profile and a sharp corner, so as to increase the strength of electric field, optimize the erasing efficiency and reliability
Data Source
AI summary
A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed.