Liquid Crystal Display Panel Via Structure Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Liquid crystal display panels face issues with high parasitic capacitance and manufacturing yield due to large non-display areas and potential connection path disruptions in the FFS mode, particularly with the use of organic insulating films and contact holes in the passivation film.
Innovation Solution
The design includes a thin film transistor substrate with a planarizing insulating film that exposes the source and drain electrodes, allowing transparent conductive films to connect directly to these electrodes, and a contact hole in the insulating film positioned above the planarizing film, reducing the non-display area and minimizing the risk of connection disruptions during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a contact hole of a passivation film is formed within the opening of an organic insulating film to expose the TFT, then the pixel electrode can be electrically connected to the drain electrode, but the opening area increases leading to a larger non-display area proportion
Solution Approach 1:
The patent transitions from a planar contact hole configuration to a three-dimensional via structure that extends vertically through multiple insulating film layers. This vertical dimensionality allows the pixel electrode to connect to the drain electrode through the thickness of the insulating films rather than requiring a large lateral opening, thereby reducing the non-display area while maintaining electrical connectivity.
Solution Approach 2:
The patent implements a nested structure where the pixel electrode is positioned within a cavity formed in the insulating films, and the via structure is nested within the insulating film layers. This nesting approach allows compact integration of the electrical connection path within the display area without expanding the lateral footprint.
2Reliability
If a contact hole of a passivation film is formed within the opening of an organic insulating film, then the pixel electrode can be electrically connected to the drain electrode, but the connection path may be cut off during manufacturing reducing yield
Solution Approach 1:
The patent designs the via structure with sufficient width and depth margins before manufacturing processes begin. The via extends through the entire thickness of the insulating films with adequate lateral spacing from edges, providing a cushion against manufacturing variations such as etching depth control and alignment tolerances. This pre-designed margin reduces the risk of connection path disruption during subsequent manufacturing steps.
Solution Approach 2:
The patent creates a localized robust connection structure at the via location with enhanced dimensions compared to other parts of the device. The via width and depth are specifically optimized at the connection point to provide superior connection reliability, while other areas maintain their original design specifications. This localized enhancement ensures connection integrity without affecting overall device performance or increasing general device complexity.
3Object-affected harmful factors
If an organic insulating film is used to reduce parasitic capacitance and achieve flatness, then display quality improves, but the film thickness must be large which complicates the structure
Solution Approach 1:
The patent divides the insulating film structure into multiple distinct layers with different functions: a first insulating film layer for electrical isolation, a planarization layer for surface flatness, and a second insulating film layer for additional isolation and mechanical support. This segmentation allows each layer to be optimized independently for its specific function, reducing parasitic capacitance through proper material selection and thickness control without requiring a single excessively thick complex layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances display quality by reducing parasitic capacitance and non-display area, thereby improving manufacturing yield and reliability of the liquid crystal display panel.
Implementation Method 1
parasitic capacitance is generated between a signal line and the electrode (lower electrode) closer to a substrate among the two electrodes
Implementation Method 2
it is desirable that the insulating film between the lower electrode and the signal line have low relative permittivity and have a large thickness
Implementation Method 3
The organic insulating film also has an advantage in capability of achieving flatness by covering level difference generated due to a thin film transistor (TFT) or the like
Data Source
AI summary
A liquid crystal display panel includes a semiconductor film, source and drain electrodes, a planarizing insulating film, first and second transparent conductive films, an insulating film, a pixel electrode, and a counter electrode. The semiconductor film overlaps a gate electrode on a substrate across a gate insulating film. The source and drain electrodes are separately provided on the semiconductor film. The planarizing insulating film includes an opening for partially exposing the source and drain electrodes on its bottom. The first and second transparent conductive films respectively come in contact with surfaces of the source and drain electrodes. The insulating film is provided on the planarizing insulating film so as to cover the opening and the first and second transparent conductive films. The pixel electrode is provided on the insulating film and is electrically connected to the drain electrode via the second transparent conductive film. The counter electrode is opposed to the pixel electrode.