Parasitic Vertical PNP Transistor in BiCMOS Using Shared CMOS Implants
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Solution Overview
Problem
Current BiCMOS process for NPN bipolar transistors requires complex and costly processes, including heavy doped collector buried layers and deep trench isolation, which are not efficiently adapted for parasitic vertical PNP transistor design, limiting their use as high-speed, high-current devices.
Innovation Solution
A parasitic vertical PNP bipolar transistor is designed using shallow trench isolation (STI) with a p-type ion implantation for the collector, shared with CMOS well implants, and a n-type ion implantation for the base, connected by heavily doped poly silicon, reducing fabrication costs and complexity without additional processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavily doped collector buried layer is used to reduce collector resistance, then collector resistance is reduced, but fabrication complexity and cost increase due to additional high dose high energy implanting and deep trench isolation processes
Solution Approach 1:
The patent merges the PNP transistor fabrication with existing CMOS well implant processes. The p-type collector region is formed using the same ion implantation process that creates the P-well for CMOS devices, eliminating the need for separate high dose high energy implanting. The shallow trench isolation structure serves dual purposes: isolating CMOS devices and forming the collector region for PNP transistors, thereby removing the need for additional deep trench isolation processes.
Solution Approach 2:
The shallow trench isolation structure is designed to perform multiple functions: it provides electrical isolation for CMOS devices, forms the collector region for PNP transistors, and enables current flow paths for both device types. This multi-functional design eliminates the need for separate specialized structures for PNP transistors, reducing overall fabrication complexity.
2Reliability
If traditional BiCMOS process is used for PNP transistor fabrication, then transistor performance is achieved, but fabrication cost increases due to additional processes
Solution Approach 1:
The patent combines PNP transistor fabrication steps with standard CMOS processing sequences. The n-type base region is formed using the same ion implantation process that creates lightly doped drain regions for NMOS devices. The emitter region is formed using existing source/drain contact processes, eliminating the need for additional specialized fabrication steps and reducing overall manufacturing cost.
Solution Approach 2:
The patent designs the PNP transistor to utilize existing doped regions created for CMOS devices. The P-well implant creates the collector, the NLDD implant creates the base, and subsequent source/drain processing creates the emitter. This self-service approach allows the PNP transistor to be formed as a byproduct of standard CMOS processing, minimizing additional fabrication costs.
3Device complexity
If shallow trench isolation is used instead of deep trench isolation, then fabrication complexity is reduced, but isolation effectiveness may be compromised
Solution Approach 1:
The shallow trench isolation structure is designed to serve dual purposes: providing electrical isolation for CMOS devices and forming the active collector region for PNP transistors. By making the isolation structure multi-functional, the patent eliminates the need for deeper isolation trenches while maintaining both isolation effectiveness and PNP transistor performance through careful doping profile design.
Solution Approach 2:
The patent modifies the doping parameters of the shallow trench isolation region to achieve both isolation and collector functionality. By controlling the implant dose, energy, and profile of the p-type ions in the STI region, the structure provides sufficient electrical isolation for CMOS while simultaneously creating the appropriate collector characteristics for high-performance PNP transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The parasitic vertical PNP bipolar transistor achieves high current gain and frequency characteristics, suitable for high-speed and high-current applications, offering a cost-effective alternative to traditional BiCMOS processes by integrating with existing NMOS and CMOS implants, and eliminating the need for buried layers and deep trench isolation.
Implementation Method 1
The P-type ion implantation is shared with the P type well implant of the CMOS, contains anti-punch through implant and Vt implant. This p-type layer connects the p-type buried layer which formed by the P type ion implanting around the collector region in the bottom of shallow trench isolation (STI). The p-type ion implanting dose range is 1e14 ̃1e16 cm−2, energy is lower than 15 Kev, and the implant impurity is boron BF2 or Indium.
Implementation Method 2
The N-type ion implant of the base region is share with the N-type lightly doped drain (NLDD) implant of the NMOS, the implant impurity is phosphorus or arsenic, the energy is range is 1-100 Kev, the dose range is 1e11-1e15 cm-2, the implant depth and dose can fit the NMOS performance.
Implementation Method 3
An emitter, which is formed by a epitaxy layer on above mentioned base region. The doping method and epitaxy method is same as the method of forming the base of NPN bipolar transistor. The thickness is less than 5000 Å. The implant species can be boron, and the boron peak concentration range is 1e17-1e20 cm−2, the thickness and ion distribution is determined by the bipolar performance.
Implementation Method 4
the collector is formed by p-type ion implanting, which is shared by the P type well implant condition of MOSFET and following the rapid thermal anneal (RTA) process to diffuse the p-type buried layer to make the two regions connected
Data Source
AI summary
A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.