Conductive Bridging Memory Device with Ion Metal Layer
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Solution Overview
Problem
The miniaturization of memory cells in planar nonvolatile semiconductor memory devices has reached its limits, making it difficult to manufacture next-generation memory devices like cross-point memory, which requires three-dimensional arrangement of memory cells, and existing technologies face challenges in reducing the leakage current between memory cells.
Innovation Solution
A conductive bridging memory device is developed with a multilayer wiring structure and resistance change layer, where ion metal layers and counter electrode layers are strategically positioned between word and bit lines, allowing for the formation of filaments that switch resistance states between high and low, enabling efficient data storage with minimal leakage current through anisotropic etching and damascene methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized in planar nonvolatile semiconductor memory devices, then storage density increases, but manufacturing becomes difficult and leakage current between memory cells increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked structure with multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) and resistance change layers positioned at different heights. This vertical stacking enables increased storage density while maintaining manufacturability through standardized layer formation processes.
Solution Approach 2:
The memory device is segmented into multiple independent memory cells formed by intersecting word lines and bit lines in a cross-point architecture. Each memory cell is defined by specific intersections of conductive layers, allowing independent addressing and reducing interference between cells, which addresses the leakage current problem while enabling high-density packing.
2Quantity of substance
If memory cells are miniaturized, then storage density increases, but leakage current between memory cells increases
Solution Approach 1:
Insulating layers are introduced as intermediary materials between adjacent conductive layers and memory cells. These insulating layers act as barriers that prevent leakage current between neighboring cells while allowing the conductive paths needed for memory operation, thus enabling high-density integration without suffering from cross-talk and leakage issues.
Solution Approach 2:
The patent applies different material properties to different regions: conductive materials (tungsten, copper) for word lines and bit lines, resistive materials for resistance change layers, and insulating materials for isolation. This local differentiation of material properties ensures that each region performs its specific function - conduction where needed, isolation where required - thereby preventing leakage current while maintaining storage density.
3Quantity of substance
If three-dimensional memory cell arrangement is implemented, then storage density increases, but device complexity increases
Solution Approach 1:
The patent employs universal formation processes for all wiring layers and resistance change layers, using the same deposition, etching, and patterning techniques throughout the three-dimensional structure. This universality of manufacturing processes reduces the complexity increase that would otherwise result from three-dimensional integration, as the same toolset and methodologies are applied at each level of the stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution facilitates the manufacturing of high-integration memory devices with reduced leakage current between memory cells, allowing for reliable data storage and easy miniaturization of memory cells without the challenges of buckling or collapse during etching.
Implementation Method 1
an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction
Implementation Method 2
dividing the ion metal layer without dividing the resistance change layer by performing anisotropic etching using the second wirings as a mask
Data Source
AI summary
According to one embodiment, a conductive bridging memory device includes a first wiring layer having a plurality of first wiring portions extending in a first direction, a second wiring layer having a plurality of second wiring portions extending in a second direction crossing the first direction, and a resistance change layer provided continuously along a plane having the first direction and the second direction between the first wiring layer and the second wiring layer. Each of the first wiring portions includes a first wiring extending in the first direction. Each of the second wiring portions includes a second wiring extending in the second direction, and an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction.