CDC Simulation System for Timing Violation Detection
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Solution Overview
Problem
Existing tools fail to accurately simulate and identify timing violations caused by Clock Domain Crossings (CDC) in Hardware Description Language (HDL) based circuit designs, particularly when dealing with asynchronous clocks, as they lack the capability to resolve violations between unrelated clock domains and often mask functional errors in unit-level simulations.
Innovation Solution
A Clock Domain Crossing (CDC) simulation system that receives a Behavioral Description Language (BDL) based circuit design, analyzes it to identify CDCs, and inserts code into a test bench to simulate and identify timing violations by monitoring asynchronous clock interactions, providing indications of setup and hold timing violations and forcing random or indeterminate values onto affected outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional unit-level simulation tools are used, then simulation speed is maintained, but timing violations in asynchronous clock domains cannot be accurately identified
Solution Approach 1:
The system segments the simulation process by inserting dedicated CDC monitoring code at specific clock domain crossing points within the test bench. This allows timing violation detection to be performed separately from the main simulation flow, enabling accurate async clock domain timing analysis without requiring full simulation slowdown
Solution Approach 2:
The patent introduces intermediary monitoring code that acts as a mediator between the asynchronous clock domains. This code captures signals from source clock domain, monitors them against destination clock domain timing requirements, and reports violations without altering the original design or requiring comprehensive simulation re-engineering
2Reliability
If comprehensive timing analysis is performed on all clock domains, then timing violation detection improves, but system complexity increases
Solution Approach 1:
The system applies local quality by inserting CDC monitoring code only at specific locations where clock domain crossings occur, rather than implementing comprehensive timing analysis across the entire design. The monitoring is localized to relevant CDC points identified by the timing analysis module, reducing overall system complexity while maintaining detection capability
Solution Approach 2:
The timing analysis module performs preliminary analysis to identify all CDC points in the design before simulation begins. This preliminary identification allows the test bench to be pre-configured with monitoring code only where needed, avoiding the complexity of dynamic analysis during simulation while ensuring complete coverage of async clock domains
3Measurement precision
If the design is altered to add monitoring code, then timing violation detection accuracy improves, but design modification effort increases
Solution Approach 1:
The patent extracts the CDC monitoring functionality from the design itself and places it in the test bench environment. By taking out the monitoring code from the design and implementing it externally in the test bench, the system achieves accurate timing violation detection without requiring any modifications to the original HDL design code
Solution Approach 2:
The system creates a copy of the monitoring logic in the test bench that mirrors the CDC points in the design. Rather than modifying the design, the test bench contains replicated monitoring code that observes design behavior, enabling detection without alteration of the original design while maintaining detection accuracy
Data Source
AI summary
According to one aspect, embodiments of the invention provide a CDC simulation system comprising a timing analysis module configured to receive a circuit design, analyze the circuit design to identify at least one CDC, and generate a report including information related to the at least one CDC, a CDC simulation module configured to communicate with the timing analysis module and to receive the report from the timing analysis module, and a test bench module configured to communicate with the CDC simulation module, to receive the circuit design, and to operate a test bench code to simulate the operation of the circuit design, wherein the CDC simulation module is further configured to edit a top level of the test bench code, based on the received report, such that the test bench module is configured to identify timing violations in the circuit design due to the at least one CDC.