Computer Aided Design TRIZ Cases
- Power Delivery Network Staple Removal for Signal Routing
Removing redundant power staples frees routing tracks for signal wires, reducing voltage drop and improving area utilization.
- Automated Netlist Loop Pipelining for Clock Frequency
A processor identifies netlist loops and applies pattern-based optimization methods to modify logic structures.
- Integrated Circuit Physical Synthesis Timing Optimization
Unified synthesis and placement processes resolve interconnect delay inaccuracies that degrade timing predictability in complex chip designs.
- RTL Power Source Hierarchy for IC Design Verification
Information structure specifies power source hierarchy in RTL designs, resolving gaps between behavioral specifications and physical implementation reliability.
- Dynamic Critical Path Detector for IC Timing
A dynamic critical path detector monitors integrated circuit timing using latches and comparators.
- IC Pattern Matching Using Anchor-Based Zone Segmentation
A method selects pattern anchors with the shortest match time estimates to search integrated circuit layouts for matching regions.
- Column-Based Transmission Gate Layout for Routing Congestion
Vertical transmission gate arrangement shares control terminals, reducing routing congestion and chip area.
- Distributed Critical Path Monitors for Dynamic Frequency Margin Recovery
Distributed critical path monitors track real-time process variations to recover frequency margin and eliminate excessive design overhead.
- RTL Netlist Equivalence Verification Automation
Automated equivalence checking compares updated RTL definitions against synthesized netlists to identify logical relation changes.
- CDC Simulation System for Timing Violation Detection
A clock domain crossing simulation system inserts monitoring code into test benches to detect timing violations in asynchronous circuit designs.
- RTL Clock-Gating Insertion via Term Clustering
A computer-implemented method for inserting clock-gating in register-transfer level designs by clustering state elements with equivalent control terms.
- Free-Space Lens Oxel Array for Wide Field of View
Discrete oxels on a reflective 3D surface maintain wide field of view while preserving manufacturing precision.
- Tessellated Routing Space Labeling for IC Design
Dynamic tessellation labels resolve complex grid constraints in integrated circuit layout.
- Waiver Geometric Elements for IC Layout Verification
Waiver geometric elements mask false errors in layout design data, eliminating repetitive manual waivers across different design entities.
- Parameterized Cell Layout Optimization for VLSI Yield
Segments schematic and physical parameters to optimize yield in VLSI designs without increasing data volume or personalization complexity.
- Semiconductor Defect Operating System for Yield Improvement
A cloud-based defect operating system aggregates wafer data to identify killer defects through critical area analysis.
- Transistor Modeling via Well Proximity Effect Calculation
A post-layout extraction tool calculates effective well proximity values using a complementary error function for integrated circuit simulation.
- VLSI Placement Method Using Routing Congestion Penalties
A placement method for integrated circuit design uses routing congestion penalties to optimize cluster positioning.
- Aggregate Slack Analysis for Circuit Timing Optimization
Analyzes aggregate slacks across logic path chains to prioritize optimization efforts, resolving timing violations before clock tree synthesis.
- Automated RTL Case-Splitting Detection for Timing Violations
An automated technique detects case-splitting opportunities in register transfer level designs to optimize critical paths.
- IC Floorplan Optimization via Interconnect Figures of Merit
Reduces signal propagation delays and design iterations by applying preliminary action and feedback mechanisms to interconnect optimization parameters.
- Timing Assistant for Dynamic Voltage Drop Analysis
A timing assistant tool predicts critical circuit paths using predictive models that account for dynamic voltage drop.
- Integrated Circuit Control Set Optimization for Placement
Hierarchical control set optimization resolves architectural limitations by reducing resource constraints and improving placement feasibility.
- Semiconductor Edge Cell Finger Integration for Density Gradient Compensation
Direct finger connections between edge and inner cells distribute pattern density gradients, reducing dishing risks without adding dummy structures.
- Spare Correction Cells for Post-Mask Timing Adjustment
Spare correction cells modify wire network connections to fix timing errors without altering the fixed chip layout.
- SOI MOS Device Modeling for Junction Capacitance
A modular SOI MOS device model separates primary transistor behavior from body junction capacitances to enhance simulation accuracy.