IC Floorplan Optimization via Interconnect Figures of Merit
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Solution Overview
Problem
The design of integrated circuits faces challenges in balancing performance, power consumption, and surface area, with increasing complexity leading to difficulties in accommodating routing paths within available metal layers, resulting in larger surface areas and longer time-to-market due to iterative design processes.
Innovation Solution
A computer-implemented method for designing a floorplan that optimizes interconnect delays and power consumption by determining logical definitions for system and logic devices, along with interconnect figures of merit, to select interconnect devices that balance computational performance, power consumption, and physical area, thereby reducing signal propagation delays and maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple iterations of physical floorplan are developed to achieve optimum values for performance, power consumption, and surface area, then the desired parameters are achieved, but the time-to-market is increased
Solution Approach 1:
The patent applies preliminary action by determining interconnect figures of merit during the logic design phase, before physical floorplan development begins. This early determination of interconnect characteristics (delay, power, area) allows for predictive optimization of routing paths without requiring multiple iterative floorplan developments, thus reducing time-to-market while achieving performance targets
2Adaptability or versatility
If the complexity of the required circuit blocks increases, then the functional capabilities are enhanced, but it becomes difficult to accommodate the routing paths within available metal layers
Solution Approach 1:
The patent introduces interconnect figures of merit as an intermediary metric that mediates between complex circuit block requirements and physical routing constraints. By evaluating and optimizing based on these figures of merit (delay, power, area), the system can handle increased circuit complexity while systematically managing routing path accommodation within available metal layers
3Ease of manufacture
If the surface area is increased to provide sufficient space for various routing paths, then the routing paths can be accommodated, but the surface area is larger than otherwise necessary
Solution Approach 1:
The patent applies parameter changes by optimizing routing paths based on interconnect figures of merit that include area constraints. By changing the optimization parameters to consider area efficiency alongside delay and power, the system achieves adequate routing path accommodation with minimized surface area, avoiding excessive layout expansion
4Reliability
If automated tools perform block timing analysis multiple times during the place-and-route process, then the timing requirements are ensured, but the quantity of iterations increases
Solution Approach 1:
The patent implements feedback by using interconnect figures of merit determined during logic design to guide and constrain the place-and-route process. This feedback mechanism allows timing analysis to be performed with predetermined interconnect characteristics, reducing the number of iterations needed while ensuring timing requirements are met through targeted optimization
Data Source
AI summary
A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design. The candidate floorplan is implemented as the integrated circuit.