Transistor Modeling via Well Proximity Effect Calculation
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Solution Overview
Problem
In CMOS integrated circuit design, the well proximity effect, which affects transistor threshold voltage due to ion scattering during implantation, is not adequately accounted for in existing modeling methods, especially in deep sub-micron processes where transistors are close to well edges, leading to inaccurate circuit designs.
Innovation Solution
A method that extracts geometry data from layout information to calculate an effective well proximity value using a complementary error function, which is then incorporated into a post-layout netlist to simulate the integrated circuit, accurately accounting for the well proximity effect on transistor threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are placed close to well edges to increase circuit density, then productivity is improved, but manufacturing precision deteriorates due to well proximity effect causing threshold voltage variations
Solution Approach 1:
The patent applies parameter changes by modifying the threshold voltage model to include well proximity effect parameters. The extraction tool calculates effective well proximity values based on geometric parameters (distance to well edges, well dimensions) and incorporates these into the threshold voltage calculation, transforming the model from a simple constant-value approach to a spatially-dependent parameter approach that accounts for ion scattering effects.
Solution Approach 2:
The patent introduces an intermediary extraction tool that acts as a mediator between the physical layout and the circuit simulator. This tool calculates effective well proximity values based on the geometric relationship between transistors and well edges, and inserts these values into the netlist as intermediary parameters that the simulator then uses to adjust threshold voltages, thereby bridging the gap between physical geometry and electrical behavior.
2Device complexity
If existing modeling methods are used without well proximity effect, then device complexity is reduced, but measurement precision deteriorates in predicting threshold voltage
Solution Approach 1:
The patent applies preliminary action by performing well proximity effect calculations during the layout extraction phase, before circuit simulation. The extraction tool pre-calculates effective well proximity values for all transistors based on their geometric relationships with well edges, and embeds these values in the netlist beforehand. This preliminary computation avoids the need for complex real-time calculations during simulation, maintaining device complexity at an acceptable level while significantly improving measurement precision.
3Manufacturing precision
If accurate well proximity modeling is implemented, then manufacturing precision is improved, but device complexity increases due to additional calculation requirements
Solution Approach 1:
The patent applies mechanics substitution by replacing complex physical modeling of ion scattering with an empirical complementary error function (erfc). Instead of simulating the actual ion implantation physics and scattering processes, the patent uses the erfc function to model the well proximity effect, which captures the essential behavior with a simple mathematical expression that is computationally efficient and easy to implement in extraction tools and simulators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more accurate simulation and design of integrated circuits by accounting for the cumulative well proximity effect, improving the prediction of threshold voltage changes and enhancing the overall design precision.
Implementation Method 1
An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function
Implementation Method 2
The well proximity effect is due to some of the ions in the implantation process scattering from the edge of the photoresist mask and being implanted in the silicon surface near the mask edge
Data Source
AI summary
An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.