RTL Clock-Gating Insertion via Term Clustering
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Solution Overview
Problem
Existing IC design automation tools defer clock-gating insertion to later stages, losing designer control and making it difficult to measure and optimize power effectiveness early in the design process.
Innovation Solution
A computer-implemented method for inserting clock-gating in RTL designs by flattening the design, identifying modules and state elements, computing clock-gating expressions, selecting traceable terms, determining equivalent terms, clustering state elements, and inserting clock-gating logic into the RTL design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If clock-gating insertion is deferred to later stages by existing EDA tools, then the design process follows conventional automation flow, but designer control is lost and power optimization effectiveness cannot be measured early
Solution Approach 1:
The patent performs clock-gating insertion at RTL design stage rather than deferring to later stages. By computing clock-gating expressions and inserting logic early in the design flow, the system enables designer control and early power optimization measurement while maintaining automation through systematic algorithms for expression computation and logic insertion.
2Ease of manufacture
If clock-gating insertion is deferred to later stages, then conventional EDA tool flow is maintained, but power effectiveness measurement and optimization become difficult early in design
Solution Approach 1:
The system inserts clock-gating logic at RTL stage to enable early power effectiveness measurement. By computing clock-gating expressions and inserting logic before implementation stages, the system allows power optimization to be measured and adjusted early in the design process while maintaining compatibility with subsequent EDA tool flows.
3Reliability
If clock-gating is optimized at backend stages, then implementation constraints are better known, but optimization scope is limited and control is reduced
Solution Approach 1:
The patent performs clock-gating optimization at RTL design stage with full design scope visibility. By computing clock-gating expressions across the entire RTL design before implementation, the system achieves broader optimization scope and greater adaptability, while still accommodating implementation constraints through iterative refinement and verification in later stages.
Data Source
AI summary
A computer-implemented method for inserting clock-gating in a register-transfer level (RTL) design is provided. The computer-implemented method includes flattening the RTL design, identifying modules and state elements in the RTL design, computing a clock-gating expression for each of the state elements of the RTL design, selecting terms of the clock-gating expression for each one of the state elements that is traceable to signals in a same one of the modules as the one of the state elements, determining which clock-gating terms are equivalent to those of other state elements in the RTL design, clustering state elements with equivalent clock-gating terms into clusters and inserting clock-gating logic, which equates to the equivalent clock-gating terms, into the RTL design for each cluster.