RTL Netlist Equivalence Verification Automation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The process of re-synthesizing a netlist to reflect changes in a circuit design is time-consuming and resource-intensive, and manual verification of equivalence between RTL and netlist changes is error-prone and computationally burdensome.
Innovation Solution
A method and toolset that automatically analyze updated RTL and netlist definitions to identify changed logical relations, selectively apply satisfiability solvers to verify equivalence only where necessary, and provide notifications for discrepancies, thereby focusing verification resources on areas requiring formal verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire netlist is re-synthesized to reflect RTL changes, then equivalence is ensured, but the process becomes time-consuming and resource-intensive
Solution Approach 1:
The patent segments the verification process by identifying and isolating only the changed logical relations in the netlist that correspond to RTL changes. Instead of verifying the entire netlist, the system divides the verification scope into specific changed regions, thereby reducing verification time while maintaining equivalence assurance for the affected portions.
Solution Approach 2:
The system applies verification resources locally to only those parts of the netlist that have changed. By analyzing the differences between initial and updated netlists, the system targets verification efforts precisely at the changed logical relations, avoiding unnecessary verification of unchanged portions and thus reducing overall verification time and computational resources.
2Measurement precision
If manual verification of equivalence is performed, then detailed analysis is possible, but the process becomes error-prone and computationally burdensome
Solution Approach 1:
The system performs automated self-verification by comparing the updated netlist against the updated RTL definition using algorithmic equivalence checking. This eliminates manual verification errors and reduces computational burden by systematically identifying changed logical relations and automatically verifying their equivalence, rather than relying on error-prone manual analysis.
Solution Approach 2:
The patent replaces manual mechanical verification processes with automated computational methods. By using software-based equivalence checking tools that algorithmically compare logical relations, the system achieves precise verification without the errors and computational burdens associated with manual analysis, substituting human effort with automated computational verification.
3Reliability
If full netlist verification is performed, then all equivalence issues are detected, but resource expenditure increases significantly
Solution Approach 1:
The system applies partial verification action by focusing only on the changed logical relations in the netlist. Instead of performing excessive full-netlist verification, the system identifies the minimal subset of changed relations that require verification, thereby detecting all relevant equivalence issues while significantly reducing computational resource expenditure on unchanged portions.
Data Source
AI summary
A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.