IC Pattern Matching Using Anchor-Based Zone Segmentation

Solution Overview

Problem

Pattern matching during integrated circuit (IC) verification is time-consuming and memory-intensive, requiring a faster and less memory-intensive approach to efficiently identify hotspots or waive good patterns from error reports.

Innovation Solution

The method involves associating IC patterns with multiple pattern anchors of different types, calculating match time estimates, and using the pattern anchor with the shortest match time estimate to search the target IC layout for matching regions, thereby reducing verification run time and memory usage. This is achieved through an IC validator system with components like an IC pattern library, anchor generator, and matching engine that utilize anchor types and match time estimates to efficiently find matching areas in the target IC layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional pattern matching is used during IC verification, then comprehensive pattern identification is achieved, but verification run time becomes excessively long and memory consumption increases

Engineering Contradiction:

Improvepattern identification accuracyVSAvoidverification run time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the IC layout verification process by dividing it into multiple zones based on anchor points. Instead of performing exhaustive pattern matching across the entire IC layout, the system divides the layout into smaller regions (first zone, second zone, etc.) and performs pattern matching only in relevant zones. This segmentation significantly reduces the search space and computational complexity while maintaining comprehensive pattern identification accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-identifying anchor points and pre-dividing the IC layout into zones before performing pattern matching. The system calculates match time estimates for different anchor types in advance and uses these pre-computed structures to guide the actual pattern matching process. This preliminary preparation reduces the time required during the actual verification phase.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If traditional pattern matching is used during IC verification, then all patterns are identified, but memory consumption becomes excessive

Engineering Contradiction:

Improvepattern identification accuracyVSAvoidmemory usage

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the IC layout verification process by dividing it into multiple zones based on anchor points. Instead of performing exhaustive pattern matching across the entire IC layout, the system divides the layout into smaller regions (first zone, second zone, etc.) and performs pattern matching only in relevant zones. This segmentation significantly reduces the search space and computational complexity while maintaining comprehensive pattern identification accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts and uses only the necessary portions of the IC layout for pattern matching by focusing on zones relevant to specific anchor points. The system identifies and processes only the portions of the layout that contain or are near anchor points, rather than loading and processing the entire layout into memory. This extraction approach reduces memory consumption while maintaining pattern identification accuracy.

Inventive Principle:

Principle #2Taking out (Extraction)

3Measurement precision

If exhaustive pattern matching is performed across the entire IC layout, then no patterns are missed, but verification productivity decreases

Engineering Contradiction:

Improvepattern detection completenessVSAvoidverification throughput

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the IC layout verification process by dividing it into multiple zones based on anchor points. Instead of performing exhaustive pattern matching across the entire IC layout, the system divides the layout into smaller regions (first zone, second zone, etc.) and performs pattern matching only in relevant zones. This segmentation significantly reduces the search space and computational complexity while maintaining comprehensive pattern identification accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a dynamic pattern matching approach where the verification process adapts to the specific characteristics of different anchor points and zones. The system dynamically adjusts the pattern matching strategy based on match time estimates calculated for different anchor types, processing zones with higher priority or shorter estimated match times first. This dynamic approach optimizes verification throughput while ensuring complete pattern detection.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11487930B2Pattern matching using anchors during integrated circuit verification

Publication Date: 2022.11.01 SYNOPSYS INC

AI summary

Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are generated for the target IC layout, and the target IC layout is searched for the IC pattern using the selected pattern anchor and the target anchors.