Spare Correction Cells for Post-Mask Timing Adjustment
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Solution Overview
Problem
In digital integrated circuit design, timing corrections are challenging in the post-mask stage as the physical layout is fixed, limiting the ability to modify key layers or add new logic units, making it difficult to address timing errors without altering the chip's layout.
Innovation Solution
A method and device that utilize spare correction cells to identify and implement timing corrections by modifying wire network connections within a defined search range, allowing for timing optimization without changing the base layer of the chip's physical layout, using spare cells such as buffer or filler cells to adjust timing without altering the existing layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If timing correction is performed in the post-mask stage after signing off and taping out, then timing errors can be corrected in the late design phase, but the physical layout cannot be modified and only upper metal connections can be changed
Solution Approach 1:
The patent segments the timing correction process into multiple stages: first identifying timing violations through simulation, then selecting appropriate correction methods (buffer insertion, cell size change, wire mesh splitting) based on the violation type and location. This segmentation allows targeted corrections without requiring global layout changes, resolving the contradiction between precision and flexibility.
Solution Approach 2:
The patent introduces an intermediary correction layer that operates between the fixed physical layout and the timing requirements. By inserting buffer units or modifying upper metal connections as intermediaries, the system can adjust timing without changing the base layout, thus maintaining both precision and adaptability.
2Manufacturing precision
If buffer units are inserted or cell size is changed to correct timing errors, then timing requirements can be met, but the complexity of the circuit increases
Solution Approach 1:
The patent applies partial correction by inserting buffer units only at specific locations where timing violations occur, rather than modifying the entire circuit. This selective approach corrects timing requirements while minimizing the increase in overall circuit complexity, as only the necessary portions are modified.
Solution Approach 2:
The patent changes parameters such as cell size and buffer unit dimensions to achieve timing correction. By adjusting these parameters rather than adding complex structural changes, the system can meet timing requirements with minimal increase in circuit complexity.
3Manufacturing precision
If wire mesh is split or upper metal connections are modified to correct timing, then timing errors can be remedied, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary identification of timing violations through simulation before actual manufacturing corrections are applied. This preliminary action allows planning of corrections in advance, selecting the least invasive methods (such as buffer insertion) that can be implemented with minimal impact on the manufacturing process.
Solution Approach 2:
Instead of modifying the physical layout to fix timing issues, the patent inverts the approach by modifying upper metal connections and adding buffer units that work with the existing layout structure. This inverted approach maintains manufacturing simplicity while achieving timing correction.
Data Source
AI summary
A method and a device for timing correction, a computing device, and a storage medium applied to an integrated circuit are provided. In the method, the integrated circuit includes normal logic cells and spare correction cells, determining a timing path with a timing error and a first normal logic cell in the timing path that does not meet a timing requirement in the integrated circuit; setting a search range around the first normal logic cell and determining at least one spare correction cell within the search range; testing and obtaining a timing result of the at least one spare correction cell used in the integrated circuit; determining a target spare correction cell according to the timing result, wherein the target spare correction cell is at least one of the at least one spare correction cell. The method for timing correction and etc. ensure the correctness of the chip design.