Integrated Circuit Physical Synthesis Timing Optimization
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Solution Overview
Problem
In the design of integrated circuits, the separation of synthesis and placement processes leads to inaccuracies in timing predictability due to significant interconnect delays, causing physical layouts to often fail to meet design criteria, necessitating repeated iterations through synthesis and placement/routing processes.
Innovation Solution
An iterative process that combines synthesis and placement in a single pass, allowing for incremental transforms that modify netlists and object placements based on current design metrics, resource availability, and timing, enabling accurate design optimization and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synthesis and placement are separated into distinct processes, then the design flow is simpler and easier to manage, but timing predictability deteriorates due to significant interconnect delays
Solution Approach 1:
The patent merges synthesis and placement into a unified process called physical synthesis, where logical transformations and physical positioning occur simultaneously. This integration allows the system to account for interconnect delays during synthesis operations, thereby maintaining timing predictability while managing design flow complexity through a coordinated approach.
Solution Approach 2:
The patent performs preliminary placement considerations during the synthesis phase itself, rather than waiting for the separate placement process. By estimating physical positions and interconnect delays early in the design flow, the system can make informed synthesis decisions that account for timing constraints before actual placement occurs.
2Productivity
If statistical models are used for interconnect delay estimation in synthesis, then the synthesis process is faster and simpler, but accuracy deteriorates leading to poor correlation with actual post-layout delays
Solution Approach 1:
The patent changes the parameters used for delay estimation from abstract statistical models to physics-based models that incorporate actual geometric parameters such as wire lengths, layer information, and interconnect characteristics. This allows for more accurate delay predictions while maintaining computational efficiency through optimized calculation methods.
Solution Approach 2:
The patent introduces an intermediary physical synthesis process that acts as a bridge between synthesis and placement. This intermediary step performs detailed interconnect delay calculations using estimated physical positions, providing more accurate feedback to the synthesis optimizer without requiring complete placement, thus improving accuracy while preserving productivity.
3Reliability
If placement is performed before synthesis optimizations, then physical constraints are considered earlier, but the number of required iterations increases due to back-annotation loops
Solution Approach 1:
The patent merges synthesis and placement into a unified physical synthesis process that performs both logical and physical optimizations simultaneously. This eliminates the need for repeated back-annotation loops by integrating physical constraint satisfaction directly into the synthesis iterations, thereby maintaining reliability while reducing total iteration time.
Data Source
AI summary
Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.