Semiconductor Defect Operating System for Yield Improvement

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Solution Overview

Problem

Current semiconductor fabrication processes face challenges in managing and diagnosing defects, particularly systematic and random defects, due to limited real-time monitoring and data sharing between IC design houses and semiconductor fabrication facilities, leading to delayed product delivery and increased costs.

Innovation Solution

The implementation of a "Semiconductor Fab's Defect Operating System" that enables the collection, processing, and analysis of defect data, allowing for real-time monitoring and diagnosis of defects through coordinate conversion, critical area analysis, and defect size calibration, facilitating collaboration between IC design houses and semiconductor fabrication facilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor Fab relies on internal engineering resources and experience to resolve defect issues, then defect diagnosis capability is maintained, but defect resolution efficiency decreases when resources are insufficient

Engineering Contradiction:
Improvedefect resolution capabilityVSAvoiddefect resolution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines the defect operating systems of multiple stakeholders (semiconductor Fab, IC design house, equipment vendor, material supplier) into a unified cloud-based platform. This merging allows aggregation of defect data from multiple sources and pooling of engineering resources, enabling more efficient defect diagnosis and resolution without each party needing to maintain full internal capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a cloud-based defect operating system as an intermediary platform that mediates between semiconductor Fab, IC design houses, equipment vendors, and material suppliers. This intermediary enables data sharing, collaborative defect analysis, and coordinated problem-solving, resolving defects more efficiently than isolated internal efforts.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If semiconductor Fab collects and shares detailed defect data with IC design house, then defect diagnosis accuracy improves, but data security and information privacy risks increase

Engineering Contradiction:
Improvedefect diagnosis accuracyVSAvoiddata security risk
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The cloud-based defect operating system serves as a secure intermediary that enables detailed defect data sharing between semiconductor Fab and IC design house while implementing access control, data encryption, and permission management. This intermediary structure allows accurate defect diagnosis through data sharing while mitigating security risks through controlled access mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If semiconductor Fab implements comprehensive real-time defect monitoring system, then defect detection capability improves, but system complexity and implementation cost increase

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidmonitoring system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The defect operating system is designed as a universal multi-functional platform that handles defect data collection, real-time monitoring, analysis, visualization, and collaborative problem-solving. By consolidating multiple functions into a single integrated system, the patent reduces overall complexity compared to implementing separate specialized systems for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements automated defect detection, classification, and prioritization algorithms that reduce manual intervention requirements. The self-service capabilities include automatic data collection from manufacturing equipment, automated defect pattern recognition, and automated generation of diagnostic reports, thereby reducing operational complexity despite enhanced monitoring capabilities.

Inventive Principle:
Principle #25Self-service

4Adaptability or versatility

If semiconductor Fab processes wafers through multiple complex manufacturing steps, then product functionality improves, but defect generation probability increases

Engineering Contradiction:
Improveproduct functionalityVSAvoiddefect generation
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements real-time feedback mechanisms where defect data from each manufacturing step is immediately captured, analyzed, and fed back to adjust process parameters. This continuous feedback loop enables early detection of defect patterns and allows for real-time process corrections, preventing defect propagation through subsequent manufacturing steps while maintaining product functionality.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10726192B2Semiconductor Fab's defect operating system and method thereof
Publication Date: 2020.07.28 ELITETECH TECH
  • US10726192B2 patent drawing
  • US10726192B2 patent drawing
  • US10726192B2 patent drawing

AI summary

The present invention relates to “an Innovative Semiconductor Fab's Defect Operating System” thereof for design house and manufacturing Fab is provided. The Innovative Semiconductor Fab's Defect Operating System comprises: receiving pluralities of defect data, IC design layout data; analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) method via a Defect Operating System located inside the Fab site; identify a killer or non-killer defect based on the open or short failure probability; sending the killer defect data to the design house via internet, FTP, etc. The design house receives the wafer testing yield data; pick the bad die information and the killer defect information for failure analysis; correlate the corresponding defect data with the wafer test data; sending the failure killer defect data to the Fab via internet, FTP, etc.; and improve the wafer yield through feed forward defect data and feedback of failure killer defect data which is an innovative “Defect Operation Platform” implementation between design house and Fab.