RTL Power Source Hierarchy for IC Design Verification
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Solution Overview
Problem
Current integrated circuit (IC) design processes lack effective incorporation of power management techniques at higher abstraction levels, leading to gaps in RTL to physical level implementation and verification, and inability to capture power shut-off capabilities, which affects functional behavior and design intent.
Innovation Solution
A method to create an information structure in computer-readable memory that specifies power source hierarchy for RTL circuit designs, including multiple function instances and power domains, allowing associations between primary and secondary power domains to represent power relationships, enabling power management at higher abstraction levels and ensuring design intent is maintained throughout the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power management techniques are implemented at the physical level (post synthesis), then power optimization is achieved, but the RTL description becomes unreliable and cannot verify the final netlist implementation
Solution Approach 1:
The patent applies preliminary action by incorporating power management specifications directly into the RTL description at the behavioral level, before physical implementation. This allows power domain definitions, power shut-off capabilities, and power-related constraints to be established early in the design process, ensuring the RTL description remains reliable throughout verification and implementation stages.
2Loss of energy
If advanced power management techniques (multiple power domains with PSO) are implemented at the physical level, then power optimization is achieved, but design intent cannot be captured in the RTL description
Solution Approach 1:
The patent defines power domains, power shut-off conditions, and power management behavior directly in the RTL description before implementation. This preliminary specification of power management intent allows verification tools to check whether the final implementation matches the original design intent, preventing loss of design information.
Solution Approach 2:
The patent enables feedback by allowing verification tools to compare the final netlist implementation against the power management specifications embedded in the RTL description. This feedback mechanism ensures that power management design intent is preserved and verified throughout the design flow.
3Loss of energy
If power management is specified only at the physical implementation stage, then power optimization is achieved, but verification at earlier RTL or gate level stages cannot perform functional verification
Solution Approach 1:
The patent enables preliminary verification by incorporating power management specifications into the RTL description at the behavioral level. This allows verification tools to perform functional verification of power management behavior at early RTL or gate level stages, rather than waiting until physical implementation.
4Loss of energy
If power shut-off capability is added to functional design, then power saving is achieved, but the assumption of uninterrupted power source is undermined
Solution Approach 1:
The patent applies segmentation by dividing the circuit into multiple power domains, each with independent power shut-off capability. This segmentation allows different portions of the design to have different power states, enabling power saving while maintaining a stable overall system architecture through hierarchical power domain organization.
Data Source
AI summary
A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.