CDR VCO Bias Tuning for Faster Frequency Lock Recovery
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Solution Overview
Problem
Existing clock and data recovery circuits face challenges in efficiently adjusting bias signals to achieve precise frequency and phase locking in serial data transmission, particularly when transitioning from a low-power state.
Innovation Solution
A method and system involving a bias signal source, a voltage-controlled oscillator, and a frequency feedback signal source, utilizing a digital-to-analog converter to adjust bias values based on termination criteria, ensuring the frequency feedback value meets a threshold, thereby optimizing the clock and data recovery circuit's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the clock is embedded in the serial data and recovered by the receiver, then the device complexity is reduced, but the measurement precision of frequency and phase locking deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the recovered clock signal is compared with the embedded clock in the serial data, and the phase detector generates error signals that feed back to adjust the VCO. This closed-loop feedback system enables precise frequency and phase locking while maintaining device complexity reduction through clock embedding.
Solution Approach 2:
The patent adjusts the VCO control voltage parameter dynamically through the phase detector output to achieve precise frequency and phase locking. By changing the control voltage parameter in response to phase errors, the system maintains high measurement precision for frequency and phase while keeping the overall device complexity low.
2Measurement precision
If bias adjustment is performed to achieve precise frequency locking, then the measurement precision improves, but the loss of time increases due to additional adjustment steps
Solution Approach 1:
The patent performs preliminary bias adjustment by setting the VCO control voltage to a predetermined initial value before the actual frequency locking process. This preliminary action reduces the time required for bias adjustment during operation, as the system starts from a pre-optimized state rather than requiring extensive real-time tuning.
Solution Approach 2:
The phase-locked loop system automatically adjusts the bias through its inherent feedback mechanism, where the phase detector continuously monitors frequency/phase errors and self-corrects the VCO control voltage. This self-service capability eliminates the need for manual or external bias adjustment, reducing time loss while maintaining high frequency locking precision.
3Adaptability or versatility
If the bias signal source is adjusted dynamically, then the adaptability improves for different frequency requirements, but the device complexity increases
Solution Approach 1:
The VCO control voltage node serves multiple functions: it controls the VCO frequency, receives feedback from the phase detector for locking, and implements bias adjustment. By making this single node multi-functional, the patent achieves frequency adaptability for different requirements without significantly increasing device complexity, as the same hardware structure handles multiple tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the accuracy and efficiency of clock and data recovery by ensuring the bias signal source settles at an optimal value, improving the circuit's ability to lock onto the correct frequency and phase of the incoming data stream.
Implementation Method 1
a voltage-controlled oscillator; a bias signal source connected to an input of the voltage-controlled oscillator
Implementation Method 2
the frequency feedback signal source includes a digital to analog converter
Data Source
AI summary
A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.